📄 tool.map.rpt
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; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; lock1.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_b1j ; Untyped ;
+------------------------------------+----------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+----------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: decoder:u2|altsyncram:reduce_or_rtl_2 ;
+------------------------------------+----------------+----------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+----------------+----------------------------------+
; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; OPERATION_MODE ; ROM ; Untyped ;
; WIDTH_A ; 2 ; Untyped ;
; WIDTHAD_A ; 10 ; Untyped ;
; NUMWORDS_A ; 1024 ; Untyped ;
; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
; ADDRESS_ACLR_A ; NONE ; Untyped ;
; OUTDATA_ACLR_A ; NONE ; Untyped ;
; WRCONTROL_ACLR_A ; NONE ; Untyped ;
; INDATA_ACLR_A ; NONE ; Untyped ;
; BYTEENA_ACLR_A ; NONE ; Untyped ;
; WIDTH_B ; 1 ; Untyped ;
; WIDTHAD_B ; 1 ; Untyped ;
; NUMWORDS_B ; 1 ; Untyped ;
; INDATA_REG_B ; CLOCK1 ; Untyped ;
; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
; ADDRESS_REG_B ; CLOCK1 ; Untyped ;
; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
; INDATA_ACLR_B ; NONE ; Untyped ;
; WRCONTROL_ACLR_B ; NONE ; Untyped ;
; ADDRESS_ACLR_B ; NONE ; Untyped ;
; OUTDATA_ACLR_B ; NONE ; Untyped ;
; RDCONTROL_ACLR_B ; NONE ; Untyped ;
; BYTEENA_ACLR_B ; NONE ; Untyped ;
; WIDTH_BYTEENA_A ; 1 ; Untyped ;
; WIDTH_BYTEENA_B ; 1 ; Untyped ;
; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
; BYTE_SIZE ; 8 ; Untyped ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
; INIT_FILE ; lock2.rtl.mif ; Untyped ;
; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
; MAXIMUM_DEPTH ; 0 ; Untyped ;
; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
; DEVICE_FAMILY ; Cyclone ; Untyped ;
; CBXI_PARAMETER ; altsyncram_c1j ; Untyped ;
+------------------------------------+----------------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/password_lock/tool.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed Aug 16 14:46:44 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off tool -c tool
Info: Found 2 design units, including 1 entities, in source file decoder.vhd
Info: Found design unit 1: decoder-arch
Info: Found entity 1: decoder
Info: Found 2 design units, including 1 entities, in source file lock.vhd
Info: Found design unit 1: lock-arch
Info: Found entity 1: lock
Info: Elaborating entity "lock" for the top level hierarchy
Info: Elaborating entity "decoder" for hierarchy "decoder:u0"
Warning: Reduced register "decoder:u2|q0[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "decoder:u1|q0[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "decoder:u0|q0[7]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
Info: Duplicate register "lockclose~reg0" merged to single register "lockopen~reg0", power-up level changed
Info: Inferred 3 megafunctions from design logic
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=1024, WIDTH_A=2) from the following design logic: "decoder:u0|reduce_or~11"
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=1024, WIDTH_A=2) from the following design logic: "decoder:u1|reduce_or~11"
Info: Inferred altsyncram megafunction (OPERATION_MODE=ROM, NUMWORDS_A=1024, WIDTH_A=2) from the following design logic: "decoder:u2|reduce_or~11"
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
Info: Found entity 1: altsyncram
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_a1j.tdf
Info: Found entity 1: altsyncram_a1j
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_b1j.tdf
Info: Found entity 1: altsyncram_b1j
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_c1j.tdf
Info: Found entity 1: altsyncram_c1j
Warning: Output pins are stuck at VCC or GND
Warning: Pin "displayh[7]" stuck at GND
Warning: Pin "displayt[7]" stuck at GND
Warning: Pin "displayo[7]" stuck at GND
Info: Implemented 189 device resources after synthesis - the final resource count might be different
Info: Implemented 33 input pins
Info: Implemented 26 output pins
Info: Implemented 124 logic cells
Info: Implemented 6 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Wed Aug 16 14:46:51 2006
Info: Elapsed time: 00:00:08
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