decoder.tan.qmsg

这是用VHDL编写的译码程序,程序简单易懂

{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "decoder:inst\|Y\[6\] sel\[2\] clk 6.400 ns register " "Info: tsu for register \"decoder:inst\|Y\[6\]\" (data pin = \"sel\[2\]\", clock pin = \"clk\") is 6.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.000 ns + Longest pin register " "Info: + Longest pin to register delay is 7.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns sel\[2\] 1 PIN PIN_5 8 " "Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_5; Fanout = 8; PIN Node = 'sel\[2\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "" { sel[2] } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 120 48 216 136 "sel\[2..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(3.300 ns) 7.000 ns decoder:inst\|Y\[6\] 2 REG LC30 1 " "Info: 2: + IC(2.200 ns) + CELL(3.300 ns) = 7.000 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst\|Y\[6\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "5.500 ns" { sel[2] decoder:inst|Y[6] } "NODE_NAME" } "" } } { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.800 ns 68.57 % " "Info: Total cell delay = 4.800 ns ( 68.57 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.200 ns 31.43 % " "Info: Total interconnect delay = 2.200 ns ( 31.43 % )" {  } {  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "7.000 ns" { sel[2] decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.000 ns" { sel[2] sel[2]~out decoder:inst|Y[6] } { 0.000ns 0.000ns 2.200ns } { 0.000ns 1.500ns 3.300ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.800 ns + " "Info: + Micro setup delay of destination is 2.800 ns" {  } { { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns clk 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 136 48 216 152 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns decoder:inst\|Y\[6\] 2 REG LC30 1 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst\|Y\[6\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "1.300 ns" { clk decoder:inst|Y[6] } "NODE_NAME" } "" } } { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "3.400 ns" { clk decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out decoder:inst|Y[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } }  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "7.000 ns" { sel[2] decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.000 ns" { sel[2] sel[2]~out decoder:inst|Y[6] } { 0.000ns 0.000ns 2.200ns } { 0.000ns 1.500ns 3.300ns } } } { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "3.400 ns" { clk decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out decoder:inst|Y[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Y\[0\] decoder:inst\|Y\[0\] 6.700 ns register " "Info: tco from clock \"clk\" to destination pin \"Y\[0\]\" through register \"decoder:inst\|Y\[0\]\" is 6.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns clk 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 136 48 216 152 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns decoder:inst\|Y\[0\] 2 REG LC13 1 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC13; Fanout = 1; REG Node = 'decoder:inst\|Y\[0\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "1.300 ns" { clk decoder:inst|Y[0] } "NODE_NAME" } "" } } { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "3.400 ns" { clk decoder:inst|Y[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out decoder:inst|Y[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.500 ns + " "Info: + Micro clock to output delay of source is 1.500 ns" {  } { { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.800 ns + Longest register pin " "Info: + Longest register to pin delay is 1.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns decoder:inst\|Y\[0\] 1 REG LC13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 1; REG Node = 'decoder:inst\|Y\[0\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "" { decoder:inst|Y[0] } "NODE_NAME" } "" } } { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Y\[0\] 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'Y\[0\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "1.800 ns" { decoder:inst|Y[0] Y[0] } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 120 344 520 136 "Y\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.800 ns 100.00 % " "Info: Total cell delay = 1.800 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "1.800 ns" { decoder:inst|Y[0] Y[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.800 ns" { decoder:inst|Y[0] Y[0] } { 0.000ns 0.000ns } { 0.000ns 1.800ns } } }  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "3.400 ns" { clk decoder:inst|Y[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out decoder:inst|Y[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "1.800 ns" { decoder:inst|Y[0] Y[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.800 ns" { decoder:inst|Y[0] Y[0] } { 0.000ns 0.000ns } { 0.000ns 1.800ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "decoder:inst\|Y\[6\] en clk -0.200 ns register " "Info: th for register \"decoder:inst\|Y\[6\]\" (data pin = \"en\", clock pin = \"clk\") is -0.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.400 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns clk 1 CLK PIN_37 8 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'clk'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "" { clk } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 136 48 216 152 "clk" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 3.400 ns decoder:inst\|Y\[6\] 2 REG LC30 1 " "Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst\|Y\[6\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "1.300 ns" { clk decoder:inst|Y[6] } "NODE_NAME" } "" } } { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.400 ns 100.00 % " "Info: Total cell delay = 3.400 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "3.400 ns" { clk decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out decoder:inst|Y[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.300 ns + " "Info: + Micro hold delay of destination is 1.300 ns" {  } { { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.100 ns) 2.100 ns en 1 PIN PIN_38 8 " "Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 8; PIN Node = 'en'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "" { en } "NODE_NAME" } "" } } { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 152 48 216 168 "en" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.200 ns) 4.900 ns decoder:inst\|Y\[6\] 2 REG LC30 1 " "Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 4.900 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst\|Y\[6\]'" {  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "2.800 ns" { en decoder:inst|Y[6] } "NODE_NAME" } "" } } { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 7 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.300 ns 67.35 % " "Info: Total cell delay = 3.300 ns ( 67.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 32.65 % " "Info: Total interconnect delay = 1.600 ns ( 32.65 % )" {  } {  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "4.900 ns" { en decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.900 ns" { en en~out decoder:inst|Y[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.100ns 1.200ns } } }  } 0}  } { { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "3.400 ns" { clk decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "3.400 ns" { clk clk~out decoder:inst|Y[6] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 2.100ns 1.300ns } } } { "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" "" { Report "D:/FPGA/work/decoder/db/decoder_cmp.qrpt" Compiler "decoder" "UNKNOWN" "V1" "D:/FPGA/work/decoder/db/decoder.quartus_db" { Floorplan "D:/FPGA/work/decoder/" "" "4.900 ns" { en decoder:inst|Y[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "4.900 ns" { en en~out decoder:inst|Y[6] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 2.100ns 1.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 13 10:12:54 2006 " "Info: Processing ended: Wed Sep 13 10:12:54 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}