decoder.map.qmsg

这是用VHDL编写的译码程序,程序简单易懂

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Sep 13 10:12:44 2006 " "Info: Processing started: Wed Sep 13 10:12:44 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off decoder -c decoder" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "decoder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file decoder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 decoder-rtl " "Info: Found design unit 1: decoder-rtl" {  } { { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 decoder " "Info: Found entity 1: decoder" {  } { { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "D:/FPGA/work/decoder/decoder.bdf " "Warning: Can't analyze file -- file D:/FPGA/work/decoder/decoder.bdf is missing" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.bdf" "" { Schematic "D:/FPGA/work/decoder/top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Info: Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "decoder decoder:inst " "Info: Elaborating entity \"decoder\" for hierarchy \"decoder:inst\"" {  } { { "top.bdf" "inst" { Schematic "D:/FPGA/work/decoder/top.bdf" { { 96 216 344 192 "inst" "" } } } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "decoder.vhd(32) " "Info: VHDL Case Statement information at decoder.vhd(32): OTHERS choice is never selected" {  } { { "decoder.vhd" "" { Text "D:/FPGA/work/decoder/decoder.vhd" 32 0 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "21 " "Info: Implemented 21 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "5 " "Info: Implemented 5 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "8 " "Info: Implemented 8 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 13 10:12:47 2006 " "Info: Processing ended: Wed Sep 13 10:12:47 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}