decoder.hier_info

这是用VHDL编写的译码程序,程序简单易懂

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Y[0] <= decoder:inst.Y[0]
Y[1] <= decoder:inst.Y[1]
Y[2] <= decoder:inst.Y[2]
Y[3] <= decoder:inst.Y[3]
Y[4] <= decoder:inst.Y[4]
Y[5] <= decoder:inst.Y[5]
Y[6] <= decoder:inst.Y[6]
Y[7] <= decoder:inst.Y[7]
clk => decoder:inst.clk
en => decoder:inst.en
sel[0] => decoder:inst.sel[0]
sel[1] => decoder:inst.sel[1]
sel[2] => decoder:inst.sel[2]


|top|decoder:inst
sel[0] => Mux~0.IN10
sel[0] => Mux~1.IN10
sel[0] => Mux~2.IN10
sel[0] => Mux~3.IN10
sel[0] => Mux~4.IN10
sel[0] => Mux~5.IN10
sel[0] => Mux~6.IN10
sel[0] => Mux~7.IN10
sel[1] => Mux~0.IN9
sel[1] => Mux~1.IN9
sel[1] => Mux~2.IN9
sel[1] => Mux~3.IN9
sel[1] => Mux~4.IN9
sel[1] => Mux~5.IN9
sel[1] => Mux~6.IN9
sel[1] => Mux~7.IN9
sel[2] => Mux~0.IN8
sel[2] => Mux~1.IN8
sel[2] => Mux~2.IN8
sel[2] => Mux~3.IN8
sel[2] => Mux~4.IN8
sel[2] => Mux~5.IN8
sel[2] => Mux~6.IN8
sel[2] => Mux~7.IN8
clk => Y[6]~reg0.CLK
clk => Y[5]~reg0.CLK
clk => Y[4]~reg0.CLK
clk => Y[3]~reg0.CLK
clk => Y[2]~reg0.CLK
clk => Y[1]~reg0.CLK
clk => Y[0]~reg0.CLK
clk => Y[7]~reg0.CLK
en => Y~0.OUTPUTSELECT
en => Y~1.OUTPUTSELECT
en => Y~2.OUTPUTSELECT
en => Y~3.OUTPUTSELECT
en => Y~4.OUTPUTSELECT
en => Y~5.OUTPUTSELECT
en => Y~6.OUTPUTSELECT
en => Y~7.OUTPUTSELECT
Y[0] <= Y[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[1] <= Y[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[2] <= Y[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[3] <= Y[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[4] <= Y[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[5] <= Y[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[6] <= Y[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
Y[7] <= Y[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE