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📄 decoder.fit.eqn

📁 这是用VHDL编写的译码程序,程序简单易懂
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_Y[6] is decoder:inst|Y[6] at LC30
B1_Y[6]_p1_out = sel[1] & !sel[0] & sel[2];
B1_Y[6]_or_out = B1_Y[6]_p1_out;
B1_Y[6]_reg_input = !(B1_Y[6]_or_out);
B1_Y[6] = DFFE(B1_Y[6]_reg_input, GLOBAL(clk), , , en);


--B1_Y[5] is decoder:inst|Y[5] at LC31
B1_Y[5]_p1_out = !sel[1] & sel[0] & sel[2];
B1_Y[5]_or_out = B1_Y[5]_p1_out;
B1_Y[5]_reg_input = !(B1_Y[5]_or_out);
B1_Y[5] = DFFE(B1_Y[5]_reg_input, GLOBAL(clk), , , en);


--B1_Y[4] is decoder:inst|Y[4] at LC32
B1_Y[4]_p1_out = !sel[1] & !sel[0] & sel[2];
B1_Y[4]_or_out = B1_Y[4]_p1_out;
B1_Y[4]_reg_input = !(B1_Y[4]_or_out);
B1_Y[4] = DFFE(B1_Y[4]_reg_input, GLOBAL(clk), , , en);


--B1_Y[3] is decoder:inst|Y[3] at LC16
B1_Y[3]_p1_out = sel[0] & sel[1] & !sel[2];
B1_Y[3]_or_out = B1_Y[3]_p1_out;
B1_Y[3]_reg_input = !(B1_Y[3]_or_out);
B1_Y[3] = DFFE(B1_Y[3]_reg_input, GLOBAL(clk), , , en);


--B1_Y[2] is decoder:inst|Y[2] at LC15
B1_Y[2]_p1_out = !sel[0] & sel[1] & !sel[2];
B1_Y[2]_or_out = B1_Y[2]_p1_out;
B1_Y[2]_reg_input = !(B1_Y[2]_or_out);
B1_Y[2] = DFFE(B1_Y[2]_reg_input, GLOBAL(clk), , , en);


--B1_Y[1] is decoder:inst|Y[1] at LC14
B1_Y[1]_p1_out = sel[0] & !sel[1] & !sel[2];
B1_Y[1]_or_out = B1_Y[1]_p1_out;
B1_Y[1]_reg_input = !(B1_Y[1]_or_out);
B1_Y[1] = DFFE(B1_Y[1]_reg_input, GLOBAL(clk), , , en);


--B1_Y[0] is decoder:inst|Y[0] at LC13
B1_Y[0]_p1_out = !sel[0] & !sel[1] & !sel[2];
B1_Y[0]_or_out = B1_Y[0]_p1_out;
B1_Y[0]_reg_input = !(B1_Y[0]_or_out);
B1_Y[0] = DFFE(B1_Y[0]_reg_input, GLOBAL(clk), , , en);


--B1_Y[7] is decoder:inst|Y[7] at LC29
B1_Y[7]_p1_out = sel[1] & sel[0] & sel[2];
B1_Y[7]_or_out = B1_Y[7]_p1_out;
B1_Y[7]_reg_input = !(B1_Y[7]_or_out);
B1_Y[7] = DFFE(B1_Y[7]_reg_input, GLOBAL(clk), , , en);


--clk is clk at PIN_37
--operation mode is input

clk = INPUT();


--en is en at PIN_38
--operation mode is input

en = INPUT();


--sel[2] is sel[2] at PIN_5
--operation mode is input

sel[2] = INPUT();


--sel[1] is sel[1] at PIN_3
--operation mode is input

sel[1] = INPUT();


--sel[0] is sel[0] at PIN_2
--operation mode is input

sel[0] = INPUT();


--Y[7] is Y[7] at PIN_21
--operation mode is output

Y[7] = OUTPUT(B1_Y[7]);


--Y[6] is Y[6] at PIN_20
--operation mode is output

Y[6] = OUTPUT(B1_Y[6]);


--Y[5] is Y[5] at PIN_19
--operation mode is output

Y[5] = OUTPUT(B1_Y[5]);


--Y[4] is Y[4] at PIN_18
--operation mode is output

Y[4] = OUTPUT(B1_Y[4]);


--Y[3] is Y[3] at PIN_15
--operation mode is output

Y[3] = OUTPUT(B1_Y[3]);


--Y[2] is Y[2] at PIN_14
--operation mode is output

Y[2] = OUTPUT(B1_Y[2]);


--Y[1] is Y[1] at PIN_13
--operation mode is output

Y[1] = OUTPUT(B1_Y[1]);


--Y[0] is Y[0] at PIN_12
--operation mode is output

Y[0] = OUTPUT(B1_Y[0]);






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