decoder.tan.rpt

这是用VHDL编写的译码程序,程序简单易懂

; N/A   ; None         ; 4.300 ns   ; en     ; decoder:inst|Y[3] ; clk      ;
; N/A   ; None         ; 4.300 ns   ; en     ; decoder:inst|Y[2] ; clk      ;
; N/A   ; None         ; 4.300 ns   ; en     ; decoder:inst|Y[1] ; clk      ;
; N/A   ; None         ; 4.300 ns   ; en     ; decoder:inst|Y[0] ; clk      ;
; N/A   ; None         ; 4.300 ns   ; en     ; decoder:inst|Y[7] ; clk      ;
+-------+--------------+------------+--------+-------------------+----------+


+---------------------------------------------------------------------------+
; tco                                                                       ;
+-------+--------------+------------+-------------------+------+------------+
; Slack ; Required tco ; Actual tco ; From              ; To   ; From Clock ;
+-------+--------------+------------+-------------------+------+------------+
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[0] ; Y[0] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[1] ; Y[1] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[2] ; Y[2] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[3] ; Y[3] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[4] ; Y[4] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[5] ; Y[5] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[6] ; Y[6] ; clk        ;
; N/A   ; None         ; 6.700 ns   ; decoder:inst|Y[7] ; Y[7] ; clk        ;
+-------+--------------+------------+-------------------+------+------------+


+---------------------------------------------------------------------------------+
; th                                                                              ;
+---------------+-------------+-----------+--------+-------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To                ; To Clock ;
+---------------+-------------+-----------+--------+-------------------+----------+
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[6] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[5] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[4] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[3] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[2] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[1] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[0] ; clk      ;
; N/A           ; None        ; -0.200 ns ; en     ; decoder:inst|Y[7] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[6] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[5] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[4] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[3] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[2] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[1] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[0] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[2] ; decoder:inst|Y[7] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[6] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[5] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[4] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[3] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[2] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[1] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[0] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[0] ; decoder:inst|Y[7] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[6] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[5] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[4] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[3] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[2] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[1] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[0] ; clk      ;
; N/A           ; None        ; -2.300 ns ; sel[1] ; decoder:inst|Y[7] ; clk      ;
+---------------+-------------+-----------+--------+-------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Sep 13 10:12:54 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off decoder -c decoder
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "decoder:inst|Y[6]" (data pin = "sel[2]", clock pin = "clk") is 6.400 ns
    Info: + Longest pin to register delay is 7.000 ns
        Info: 1: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = PIN_5; Fanout = 8; PIN Node = 'sel[2]'
        Info: 2: + IC(2.200 ns) + CELL(3.300 ns) = 7.000 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst|Y[6]'
        Info: Total cell delay = 4.800 ns ( 68.57 % )
        Info: Total interconnect delay = 2.200 ns ( 31.43 % )
    Info: + Micro setup delay of destination is 2.800 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst|Y[6]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
Info: tco from clock "clk" to destination pin "Y[0]" through register "decoder:inst|Y[0]" is 6.700 ns
    Info: + Longest clock path from clock "clk" to source register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC13; Fanout = 1; REG Node = 'decoder:inst|Y[0]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.500 ns
    Info: + Longest register to pin delay is 1.800 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC13; Fanout = 1; REG Node = 'decoder:inst|Y[0]'
        Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'Y[0]'
        Info: Total cell delay = 1.800 ns ( 100.00 % )
Info: th for register "decoder:inst|Y[6]" (data pin = "en", clock pin = "clk") is -0.200 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_37; Fanout = 8; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(1.300 ns) = 3.400 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst|Y[6]'
        Info: Total cell delay = 3.400 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 4.900 ns
        Info: 1: + IC(0.000 ns) + CELL(2.100 ns) = 2.100 ns; Loc. = PIN_38; Fanout = 8; PIN Node = 'en'
        Info: 2: + IC(1.600 ns) + CELL(1.200 ns) = 4.900 ns; Loc. = LC30; Fanout = 1; REG Node = 'decoder:inst|Y[6]'
        Info: Total cell delay = 3.300 ns ( 67.35 % )
        Info: Total interconnect delay = 1.600 ns ( 32.65 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Sep 13 10:12:54 2006
    Info: Elapsed time: 00:00:01