top.vo

这是用VHDL编写的FPGA与计算机进行串口通信的程序和一个LED程序

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 5.0 Build 148 04/26/2005 SJ Full Version"

// DATE "10/23/2006 13:02:30"

// 
// Device: Altera EP1C12Q240C8 Package PQFP240
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	top (
	clk,
	display);
input 	clk;
output 	[7:0] display;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("top_v.sdo");
// synopsys translate_on

wire \clk~combout ;
wire \inst1|add~491 ;
wire \inst1|temp1[0] ;
wire \inst1|add~493 ;
wire \inst1|add~493COUT1_502 ;
wire \inst1|add~486 ;
wire \inst1|temp1[1] ;
wire \inst1|add~488 ;
wire \inst1|add~481 ;
wire \inst1|temp1[2] ;
wire \inst1|add~483 ;
wire \inst1|add~483COUT1_503 ;
wire \inst1|add~476 ;
wire \inst1|temp1[3] ;
wire \inst1|add~478 ;
wire \inst1|add~478COUT1_504 ;
wire \inst1|add~471 ;
wire \inst1|temp1[4] ;
wire \inst1|add~473 ;
wire \inst1|add~473COUT1_505 ;
wire \inst1|add~466 ;
wire \inst1|temp1[5] ;
wire \inst1|add~468 ;
wire \inst1|add~468COUT1_506 ;
wire \inst1|add~461 ;
wire \inst1|temp1[6] ;
wire \inst1|add~463 ;
wire \inst1|add~456 ;
wire \inst1|temp1[7] ;
wire \inst1|add~458 ;
wire \inst1|add~458COUT1_507 ;
wire \inst1|add~446 ;
wire \inst1|temp1[8] ;
wire \inst1|add~448 ;
wire \inst1|add~448COUT1_508 ;
wire \inst1|add~441 ;
wire \inst1|temp1[9] ;
wire \inst1|add~443 ;
wire \inst1|add~443COUT1_509 ;
wire \inst1|add~436 ;
wire \inst1|temp1[10] ;
wire \inst1|add~438 ;
wire \inst1|add~438COUT1_510 ;
wire \inst1|add~451 ;
wire \inst1|temp1[11] ;
wire \inst1|add~453 ;
wire \inst1|add~431 ;
wire \inst1|temp1[12] ;
wire \inst1|add~433 ;
wire \inst1|add~433COUT1_511 ;
wire \inst1|add~426 ;
wire \inst1|temp1[13] ;
wire \inst1|add~428 ;
wire \inst1|add~428COUT1_512 ;
wire \inst1|add~421 ;
wire \inst1|temp1[14] ;
wire \inst1|add~423 ;
wire \inst1|add~423COUT1_513 ;
wire \inst1|add~416 ;
wire \inst1|temp1[15] ;
wire \inst1|add~418 ;
wire \inst1|add~418COUT1_514 ;
wire \inst1|add~411 ;
wire \inst1|temp1[16] ;
wire \inst1|add~413 ;
wire \inst1|add~396 ;
wire \inst1|temp1[17] ;
wire \inst1|add~398 ;
wire \inst1|add~398COUT1_515 ;
wire \inst1|add~406 ;
wire \inst1|temp1[18] ;
wire \inst1|add~408 ;
wire \inst1|add~408COUT1_516 ;
wire \inst1|add~401 ;
wire \inst1|temp1[19] ;
wire \inst1|add~403 ;
wire \inst1|add~403COUT1_517 ;
wire \inst1|add~391 ;
wire \inst1|temp1[20] ;
wire \inst1|add~393 ;
wire \inst1|add~393COUT1_518 ;
wire \inst1|add~386 ;
wire \inst1|temp1[21] ;
wire \inst1|add~388 ;
wire \inst1|add~381 ;
wire \inst1|temp1[22] ;
wire \inst1|add~383 ;
wire \inst1|add~383COUT1_519 ;
wire \inst1|add~376 ;
wire \inst1|temp1[23] ;
wire \inst1|add~378 ;
wire \inst1|add~378COUT1_520 ;
wire \inst1|add~496 ;
wire \inst1|temp1[24] ;
wire \inst1|reduce_nor~204 ;
wire \inst1|reduce_nor~201 ;
wire \inst1|reduce_nor~200 ;
wire \inst1|reduce_nor~199 ;
wire \inst1|reduce_nor~202 ;
wire \inst1|reduce_nor~203 ;
wire \inst1|reduce_nor~205 ;
wire \inst1|reduce_nor~0 ;
wire \inst1|clk1hz ;
wire \inst|temp[0] ;
wire \inst|temp[0]~85 ;
wire \inst|temp[0]~85COUT1_89 ;
wire \inst|temp[1] ;
wire \inst|temp[1]~81 ;
wire \inst|temp[1]~81COUT1_90 ;
wire \inst|temp[2] ;
wire \inst|temp[2]~77 ;
wire \inst|temp[2]~77COUT1_91 ;
wire \inst|temp[3] ;
wire \inst|temp[3]~73 ;
wire \inst|temp[3]~73COUT1 ;
wire \inst|temp[4] ;
wire \inst|temp[4]~69 ;
wire \inst|temp[5] ;
wire \inst|temp[5]~65 ;
wire \inst|temp[5]~65COUT1_92 ;
wire \inst|temp[6] ;
wire \inst|temp[6]~61 ;
wire \inst|temp[6]~61COUT1_93 ;
wire \inst|temp[7] ;


// atom is at PIN_153
cyclone_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X8_Y12_N3
cyclone_lcell \inst1|add~491_I (
// Equation(s):
// \inst1|add~491  = !\inst1|temp1[0] 
// \inst1|add~493  = CARRY(\inst1|temp1[0] )
// \inst1|add~493COUT1_502  = CARRY(\inst1|temp1[0] )

	.clk(gnd),
	.dataa(\inst1|temp1[0] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add~491 ),
	.regout(),
	.cout(),
	.cout0(\inst1|add~493 ),
	.cout1(\inst1|add~493COUT1_502 ));
// synopsys translate_off
defparam \inst1|add~491_I .operation_mode = "arithmetic";
defparam \inst1|add~491_I .synch_mode = "off";
defparam \inst1|add~491_I .register_cascade_mode = "off";
defparam \inst1|add~491_I .sum_lutc_input = "datac";
defparam \inst1|add~491_I .lut_mask = "55AA";
defparam \inst1|add~491_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X8_Y12_N1
cyclone_lcell \inst1|temp1[0]~I (
// Equation(s):
// \inst1|temp1[0]  = DFFEAS(\inst1|add~491 , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst1|add~491 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|temp1[0] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst1|temp1[0]~I .operation_mode = "normal";
defparam \inst1|temp1[0]~I .synch_mode = "off";
defparam \inst1|temp1[0]~I .register_cascade_mode = "off";
defparam \inst1|temp1[0]~I .sum_lutc_input = "datac";
defparam \inst1|temp1[0]~I .lut_mask = "FF00";
defparam \inst1|temp1[0]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X8_Y12_N4
cyclone_lcell \inst1|add~486_I (
// Equation(s):
// \inst1|add~486  = \inst1|temp1[1]  $ (\inst1|add~493 )
// \inst1|add~488  = CARRY(!\inst1|add~493COUT1_502  # !\inst1|temp1[1] )

	.clk(gnd),
	.dataa(\inst1|temp1[1] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\inst1|add~493 ),
	.cin1(\inst1|add~493COUT1_502 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add~486 ),
	.regout(),
	.cout(\inst1|add~488 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst1|add~486_I .operation_mode = "arithmetic";
defparam \inst1|add~486_I .synch_mode = "off";
defparam \inst1|add~486_I .register_cascade_mode = "off";
defparam \inst1|add~486_I .sum_lutc_input = "cin";
defparam \inst1|add~486_I .lut_mask = "5A5F";
defparam \inst1|add~486_I .cin0_used = "true";
defparam \inst1|add~486_I .cin1_used = "true";
defparam \inst1|add~486_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X9_Y12_N2
cyclone_lcell \inst1|temp1[1]~I (
// Equation(s):
// \inst1|temp1[1]  = DFFEAS(\inst1|add~486 , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst1|add~486 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|temp1[1] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst1|temp1[1]~I .operation_mode = "normal";
defparam \inst1|temp1[1]~I .synch_mode = "off";
defparam \inst1|temp1[1]~I .register_cascade_mode = "off";
defparam \inst1|temp1[1]~I .sum_lutc_input = "datac";
defparam \inst1|temp1[1]~I .lut_mask = "FF00";
defparam \inst1|temp1[1]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X8_Y12_N5
cyclone_lcell \inst1|add~481_I (
// Equation(s):
// \inst1|add~481  = \inst1|temp1[2]  $ !\inst1|add~488 
// \inst1|add~483  = CARRY(\inst1|temp1[2]  & !\inst1|add~488 )
// \inst1|add~483COUT1_503  = CARRY(\inst1|temp1[2]  & !\inst1|add~488 )

	.clk(gnd),
	.dataa(vcc),
	.datab(\inst1|temp1[2] ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\inst1|add~488 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add~481 ),
	.regout(),
	.cout(),
	.cout0(\inst1|add~483 ),
	.cout1(\inst1|add~483COUT1_503 ));
// synopsys translate_off
defparam \inst1|add~481_I .operation_mode = "arithmetic";
defparam \inst1|add~481_I .synch_mode = "off";
defparam \inst1|add~481_I .register_cascade_mode = "off";
defparam \inst1|add~481_I .sum_lutc_input = "cin";
defparam \inst1|add~481_I .lut_mask = "C30C";
defparam \inst1|add~481_I .cin_used = "true";
defparam \inst1|add~481_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at LC_X8_Y12_N0
cyclone_lcell \inst1|temp1[2]~I (
// Equation(s):
// \inst1|temp1[2]  = DFFEAS(\inst1|add~481 , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(vcc),
	.datac(vcc),
	.datad(\inst1|add~481 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\inst1|temp1[2] ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \inst1|temp1[2]~I .operation_mode = "normal";
defparam \inst1|temp1[2]~I .synch_mode = "off";
defparam \inst1|temp1[2]~I .register_cascade_mode = "off";
defparam \inst1|temp1[2]~I .sum_lutc_input = "datac";
defparam \inst1|temp1[2]~I .lut_mask = "FF00";
defparam \inst1|temp1[2]~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC_X8_Y12_N6
cyclone_lcell \inst1|add~476_I (
// Equation(s):
// \inst1|add~476  = \inst1|temp1[3]  $ ((!\inst1|add~488  & \inst1|add~483 ) # (\inst1|add~488  & \inst1|add~483COUT1_503 ))
// \inst1|add~478  = CARRY(!\inst1|add~483  # !\inst1|temp1[3] )
// \inst1|add~478COUT1_504  = CARRY(!\inst1|add~483COUT1_503  # !\inst1|temp1[3] )

	.clk(gnd),
	.dataa(\inst1|temp1[3] ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\inst1|add~488 ),
	.cin0(\inst1|add~483 ),
	.cin1(\inst1|add~483COUT1_503 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\inst1|add~476 ),
	.regout(),
	.cout(),
	.cout0(\inst1|add~478 ),
	.cout1(\inst1|add~478COUT1_504 ));
// synopsys translate_off