📄 loadpw.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\dds2\dds\loadpw.rpt
loadpw
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 6/ 96( 6%) 0/ 48( 0%) 5/ 48( 10%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\dds2\dds\loadpw.rpt
loadpw
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 SYSCLK
Device-Specific Information: f:\dds2\dds\loadpw.rpt
loadpw
** EQUATIONS **
PHASEWORD0 : INPUT;
PHASEWORD1 : INPUT;
PHASEWORD2 : INPUT;
PHASEWORD3 : INPUT;
PHASEWORD4 : INPUT;
PHASEWORD5 : INPUT;
PHASEWORD6 : INPUT;
PHASEWORD7 : INPUT;
PWWRN : INPUT;
RESETN : INPUT;
SYSCLK : INPUT;
-- Node name is ':30' = 'load'
-- Equation name is 'load', location is LC2_A20, type is buried.
load = DFFE( _EQ001, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ001 = pwwrnm & !pwwrns & !RESETN;
-- Node name is ':38' = 'phswd0'
-- Equation name is 'phswd0', location is LC2_A24, type is buried.
phswd0 = DFFE( _EQ002, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ002 = load & PHASEWORD0 & !RESETN
# !load & phswd0 & !RESETN;
-- Node name is ':37' = 'phswd1'
-- Equation name is 'phswd1', location is LC8_A20, type is buried.
phswd1 = DFFE( _EQ003, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ003 = load & PHASEWORD1 & !RESETN
# !load & phswd1 & !RESETN;
-- Node name is ':36' = 'phswd2'
-- Equation name is 'phswd2', location is LC1_A24, type is buried.
phswd2 = DFFE( _EQ004, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ004 = load & PHASEWORD2 & !RESETN
# !load & phswd2 & !RESETN;
-- Node name is ':35' = 'phswd3'
-- Equation name is 'phswd3', location is LC1_A20, type is buried.
phswd3 = DFFE( _EQ005, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ005 = load & PHASEWORD3 & !RESETN
# !load & phswd3 & !RESETN;
-- Node name is ':34' = 'phswd4'
-- Equation name is 'phswd4', location is LC3_A20, type is buried.
phswd4 = DFFE( _EQ006, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ006 = load & PHASEWORD4 & !RESETN
# !load & phswd4 & !RESETN;
-- Node name is ':33' = 'phswd5'
-- Equation name is 'phswd5', location is LC7_A20, type is buried.
phswd5 = DFFE( _EQ007, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ007 = load & PHASEWORD5 & !RESETN
# !load & phswd5 & !RESETN;
-- Node name is ':32' = 'phswd6'
-- Equation name is 'phswd6', location is LC5_A20, type is buried.
phswd6 = DFFE( _EQ008, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ008 = load & PHASEWORD6 & !RESETN
# !load & phswd6 & !RESETN;
-- Node name is ':31' = 'phswd7'
-- Equation name is 'phswd7', location is LC4_A24, type is buried.
phswd7 = DFFE( _EQ009, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ009 = load & PHASEWORD7 & !RESETN
# !load & phswd7 & !RESETN;
-- Node name is ':28' = 'pwwrnm'
-- Equation name is 'pwwrnm', location is LC4_A20, type is buried.
pwwrnm = DFFE( _EQ010, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ010 = RESETN
# PWWRN;
-- Node name is ':29' = 'pwwrns'
-- Equation name is 'pwwrns', location is LC6_A20, type is buried.
pwwrns = DFFE( _EQ011, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ011 = pwwrnm
# RESETN;
-- Node name is 'SYNCPHSWD0'
-- Equation name is 'SYNCPHSWD0', type is output
SYNCPHSWD0 = phswd0;
-- Node name is 'SYNCPHSWD1'
-- Equation name is 'SYNCPHSWD1', type is output
SYNCPHSWD1 = phswd1;
-- Node name is 'SYNCPHSWD2'
-- Equation name is 'SYNCPHSWD2', type is output
SYNCPHSWD2 = phswd2;
-- Node name is 'SYNCPHSWD3'
-- Equation name is 'SYNCPHSWD3', type is output
SYNCPHSWD3 = phswd3;
-- Node name is 'SYNCPHSWD4'
-- Equation name is 'SYNCPHSWD4', type is output
SYNCPHSWD4 = phswd4;
-- Node name is 'SYNCPHSWD5'
-- Equation name is 'SYNCPHSWD5', type is output
SYNCPHSWD5 = phswd5;
-- Node name is 'SYNCPHSWD6'
-- Equation name is 'SYNCPHSWD6', type is output
SYNCPHSWD6 = phswd6;
-- Node name is 'SYNCPHSWD7'
-- Equation name is 'SYNCPHSWD7', type is output
SYNCPHSWD7 = phswd7;
Project Information f:\dds2\dds\loadpw.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,369K
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