📄 phasea.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
21 - - B -- OUTPUT 0 1 0 0 COS
28 - - C -- OUTPUT 0 1 0 0 PHASE0
29 - - C -- OUTPUT 0 1 0 0 PHASE1
27 - - C -- OUTPUT 0 1 0 0 PHASE2
9 - - - 02 OUTPUT 0 1 0 0 PHASE3
16 - - A -- OUTPUT 0 1 0 0 PHASE4
5 - - - 05 OUTPUT 0 1 0 0 PHASE5
23 - - B -- OUTPUT 0 1 0 0 PHASE6
24 - - B -- OUTPUT 0 1 0 0 PHASE7
25 - - B -- OUTPUT 0 1 0 0 SIN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - B 04 OR2 2 2 0 2 |lpm_add_sub:lpm_add_1|addcore:adder|pcarry1
- 7 - B 04 OR2 1 2 0 2 |lpm_add_sub:lpm_add_1|addcore:adder|pcarry2
- 4 - B 04 OR2 1 2 0 2 |lpm_add_sub:lpm_add_1|addcore:adder|pcarry3
- 1 - B 07 OR2 1 2 0 2 |lpm_add_sub:lpm_add_1|addcore:adder|pcarry4
- 4 - B 07 OR2 1 2 0 2 |lpm_add_sub:lpm_add_1|addcore:adder|pcarry5
- 1 - B 04 AND2 1 1 0 1 |lpm_add_sub:lpm_add_1|addcore:adder|:114
- 7 - B 07 OR2 1 3 0 2 |lpm_add_sub:lpm_add_1|addcore:adder|:162
- 6 - B 07 OR2 1 1 0 1 |lpm_add_sub:lpm_add_1|:147
- 3 - B 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|pcarry0
- 5 - B 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|pcarry1
- 7 - B 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|pcarry2
- 1 - B 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|pcarry3
- 6 - A 06 OR2 1 2 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|pcarry4
- 3 - A 09 OR2 1 2 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|pcarry5
- 6 - A 09 OR2 1 3 0 2 |lpm_add_sub:lpm_add_2|addcore:adder|:162
- 5 - A 09 OR2 1 1 0 1 |lpm_add_sub:lpm_add_2|:147
- 2 - A 12 OR2 1 2 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|pcarry0
- 5 - A 12 OR2 1 2 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|pcarry1
- 7 - A 12 OR2 1 2 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|pcarry2
- 4 - A 12 OR2 1 2 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|pcarry3
- 2 - A 06 OR2 1 2 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|pcarry4
- 2 - C 08 OR2 1 2 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|pcarry5
- 6 - C 08 OR2 1 3 0 2 |lpm_add_sub:lpm_add_3|addcore:adder|:162
- 5 - C 08 OR2 1 1 0 1 |lpm_add_sub:lpm_add_3|:147
- 4 - C 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry0
- 6 - C 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry1
- 7 - C 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry2
- 2 - C 01 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry3
- 4 - A 06 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry4
- 3 - B 06 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry5
- 7 - B 06 OR2 1 2 0 2 |lpm_add_sub:lpm_add_4|addcore:adder|pcarry6
- 8 - B 07 DFFE + 1 1 0 2 pipe17 (:45)
- 5 - B 07 DFFE + 2 1 0 1 pipe16 (:46)
- 3 - B 07 DFFE + 2 1 0 1 pipe15 (:47)
- 5 - B 06 DFFE + 2 1 0 1 pipe14 (:48)
- 8 - B 04 DFFE + 2 1 0 1 pipe13 (:49)
- 6 - B 04 DFFE + 2 1 0 1 pipe12 (:50)
- 2 - B 04 DFFE + 2 1 0 1 pipe11 (:51)
- 3 - B 04 DFFE + 2 0 0 2 pipe10 (:52)
- 7 - A 09 DFFE + 1 1 0 2 pipe27 (:71)
- 4 - A 09 DFFE + 2 1 0 1 pipe26 (:72)
- 2 - A 09 DFFE + 2 1 0 1 pipe25 (:73)
- 3 - A 06 DFFE + 2 1 0 1 pipe24 (:74)
- 8 - B 01 DFFE + 2 1 0 1 pipe23 (:75)
- 6 - B 01 DFFE + 2 1 0 1 pipe22 (:76)
- 4 - B 01 DFFE + 2 1 0 1 pipe21 (:77)
- 2 - B 01 DFFE + 2 1 0 1 pipe20 (:78)
- 2 - B 07 DFFE + 2 2 0 2 pipec1 (:88)
- 7 - C 08 DFFE + 1 1 0 2 pipe37 (:97)
- 3 - C 08 DFFE + 2 1 0 1 pipe36 (:98)
- 1 - C 08 DFFE + 2 1 0 1 pipe35 (:99)
- 5 - A 06 DFFE + 2 1 0 1 pipe34 (:100)
- 8 - A 12 DFFE + 2 1 0 1 pipe33 (:101)
- 6 - A 12 DFFE + 2 1 0 1 pipe32 (:102)
- 3 - A 12 DFFE + 2 1 0 1 pipe31 (:103)
- 1 - A 12 DFFE + 2 1 0 1 pipe30 (:104)
- 1 - A 09 DFFE + 2 2 0 2 pipec2 (:114)
- 8 - B 06 DFFE +s 2 1 1 0 pipe47~1 (~123~1)
- 6 - B 06 DFFE + 2 1 1 1 pipe47 (:123)
- 4 - B 06 DFFE + 2 1 1 2 pipe46 (:124)
- 2 - B 06 DFFE + 2 1 1 1 pipe45 (:125)
- 1 - A 06 DFFE + 2 1 1 1 pipe44 (:126)
- 8 - C 01 DFFE + 2 1 1 1 pipe43 (:127)
- 1 - C 01 DFFE + 2 1 1 1 pipe42 (:128)
- 5 - C 01 DFFE + 2 1 1 1 pipe41 (:129)
- 3 - C 01 DFFE + 2 1 1 1 pipe40 (:130)
- 4 - C 08 DFFE + 2 2 0 2 pipec3 (:140)
- 1 - B 06 OR2 0 2 1 0 :1018
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 8/ 48( 16%) 0/ 48( 0%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
B: 7/ 96( 7%) 12/ 48( 25%) 0/ 48( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
C: 8/ 96( 8%) 4/ 48( 8%) 0/ 48( 0%) 6/16( 37%) 3/16( 18%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 36 SYSCLK
Device-Specific Information: f:\dds2\dds\phasea.rpt
phasea
** EQUATIONS **
RESETN : INPUT;
SYNCFREQ0 : INPUT;
SYNCFREQ1 : INPUT;
SYNCFREQ2 : INPUT;
SYNCFREQ3 : INPUT;
SYNCFREQ4 : INPUT;
SYNCFREQ5 : INPUT;
SYNCFREQ6 : INPUT;
SYNCFREQ7 : INPUT;
SYNCFREQ8 : INPUT;
SYNCFREQ9 : INPUT;
SYNCFREQ10 : INPUT;
SYNCFREQ11 : INPUT;
SYNCFREQ12 : INPUT;
SYNCFREQ13 : INPUT;
SYNCFREQ14 : INPUT;
SYNCFREQ15 : INPUT;
SYNCFREQ16 : INPUT;
SYNCFREQ17 : INPUT;
SYNCFREQ18 : INPUT;
SYNCFREQ19 : INPUT;
SYNCFREQ20 : INPUT;
SYNCFREQ21 : INPUT;
SYNCFREQ22 : INPUT;
SYNCFREQ23 : INPUT;
SYNCFREQ24 : INPUT;
SYNCFREQ25 : INPUT;
SYNCFREQ26 : INPUT;
SYNCFREQ27 : INPUT;
SYNCFREQ28 : INPUT;
SYNCFREQ29 : INPUT;
SYNCFREQ30 : INPUT;
SYNCFREQ31 : INPUT;
SYSCLK : INPUT;
-- Node name is 'COS'
-- Equation name is 'COS', type is output
COS = !_LC1_B6;
-- Node name is 'PHASE0'
-- Equation name is 'PHASE0', type is output
PHASE0 = pipe40;
-- Node name is 'PHASE1'
-- Equation name is 'PHASE1', type is output
PHASE1 = pipe41;
-- Node name is 'PHASE2'
-- Equation name is 'PHASE2', type is output
PHASE2 = pipe42;
-- Node name is 'PHASE3'
-- Equation name is 'PHASE3', type is output
PHASE3 = pipe43;
-- Node name is 'PHASE4'
-- Equation name is 'PHASE4', type is output
PHASE4 = pipe44;
-- Node name is 'PHASE5'
-- Equation name is 'PHASE5', type is output
PHASE5 = pipe45;
-- Node name is 'PHASE6'
-- Equation name is 'PHASE6', type is output
PHASE6 = pipe46;
-- Node name is 'PHASE7'
-- Equation name is 'PHASE7', type is output
PHASE7 = pipe47;
-- Node name is ':88' = 'pipec1'
-- Equation name is 'pipec1', location is LC2_B7, type is buried.
pipec1 = DFFE( _EQ001, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ001 = !_LC7_B7 & pipe17 & !RESETN & SYNCFREQ7
# _LC7_B7 & !pipe17 & !RESETN & !SYNCFREQ7;
-- Node name is ':114' = 'pipec2'
-- Equation name is 'pipec2', location is LC1_A9, type is buried.
pipec2 = DFFE( _EQ002, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ002 = !_LC6_A9 & pipe27 & !RESETN & SYNCFREQ15
# _LC6_A9 & !pipe27 & !RESETN & !SYNCFREQ15;
-- Node name is ':140' = 'pipec3'
-- Equation name is 'pipec3', location is LC4_C8, type is buried.
pipec3 = DFFE( _EQ003, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ003 = !_LC6_C8 & pipe37 & !RESETN & SYNCFREQ23
# _LC6_C8 & !pipe37 & !RESETN & !SYNCFREQ23;
-- Node name is ':52' = 'pipe10'
-- Equation name is 'pipe10', location is LC3_B4, type is buried.
pipe10 = DFFE( _EQ004, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ004 = pipe10 & !RESETN & !SYNCFREQ0
# !pipe10 & !RESETN & SYNCFREQ0;
-- Node name is ':51' = 'pipe11'
-- Equation name is 'pipe11', location is LC2_B4, type is buried.
pipe11 = DFFE( _EQ005, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ005 = _LC1_B4 & pipe11 & !RESETN & SYNCFREQ1
# !_LC1_B4 & pipe11 & !RESETN & !SYNCFREQ1
# _LC1_B4 & !pipe11 & !RESETN & !SYNCFREQ1
# !_LC1_B4 & !pipe11 & !RESETN & SYNCFREQ1;
-- Node name is ':50' = 'pipe12'
-- Equation name is 'pipe12', location is LC6_B4, type is buried.
pipe12 = DFFE( _EQ006, GLOBAL( SYSCLK), VCC, VCC, VCC);
_EQ006 = _LC5_B4 & pipe12 & !RESETN & SYNCFREQ2
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