zuma.vhd

来自「这是一个用VHDL语言编写的并口转串口程序」· VHDL 代码 · 共 35 行

LIBRARY IEEE; 
 USE IEEE.std_logic_1164.ALL;

ENTITY intseg7 IS
   port(
        datain:in std_logic_vector(6 downto 0);
        dataout:out std_logic_vector(3 downto 0));
end intseg7;

Architecture rlt_intseg7 of intseg7 IS


BEGIN
  PROCESS(datain)
   VARIABLE  datatemp	: std_logic_vector(3 downto 0);
   BEGIN
     CASE  datain IS 
WHEN "0110000"=>datatemp :="0001";--1
WHEN "1101101"=>datatemp :="0010";--2
WHEN "1111001"=>datatemp :="00111";
WHEN "0110011"=>datatemp :="0100";
WHEN "1011011"=>datatemp :="0101";
WHEN "1011111"=>datatemp :="0110";
WHEN "1110000"=>datatemp :="0111";
WHEN "1111111"=>datatemp :="1000";
WHEN "1111011"=>datatemp :="1001";---9
WHEN "1111110"=>datatemp :="0000";---0
WHEN OTHERS=>datatemp:="1111";             --－不存在
 
    END CASE;
   dataout<=datatemp;
 END PROCESS;
END rlt_intseg7;