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📄 item_new2.vho

📁 对硅微谐振式加速度计的数据采集电路开展研究工作
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--	sum_lutc_input => "cin",
--	lut_mask => "5A5F",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[1]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => \u1|num_clk_s[1]\,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => \u1|num_clk_s[0]~152\,
	cin1 => \u1|num_clk_s[0]~152COUT1_249\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[1]~I_modesel\,
	regout => \u1|num_clk_s[1]\,
	cout0 => \u1|num_clk_s[1]~160\,
	cout1 => \u1|num_clk_s[1]~160COUT1_251\);

\u1|num_clk_s[2]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[2]\ = DFFEAS(\u1|num_clk_s[2]\ $ !\u1|num_clk_s[1]~160\, GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[2]~172\ = CARRY(\u1|num_clk_s[2]\ & !\u1|num_clk_s[1]~160\)
-- \u1|num_clk_s[2]~172COUT1_253\ = CARRY(\u1|num_clk_s[2]\ & !\u1|num_clk_s[1]~160COUT1_251\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "C30C",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[2]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => VCC,
	datab => \u1|num_clk_s[2]\,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => \u1|num_clk_s[1]~160\,
	cin1 => \u1|num_clk_s[1]~160COUT1_251\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[2]~I_modesel\,
	regout => \u1|num_clk_s[2]\,
	cout0 => \u1|num_clk_s[2]~172\,
	cout1 => \u1|num_clk_s[2]~172COUT1_253\);

\u1|num_clk_s[3]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[3]\ = DFFEAS(\u1|num_clk_s[3]\ $ (\u1|num_clk_s[2]~172\), GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[3]~184\ = CARRY(!\u1|num_clk_s[2]~172\ # !\u1|num_clk_s[3]\)
-- \u1|num_clk_s[3]~184COUT1_255\ = CARRY(!\u1|num_clk_s[2]~172COUT1_253\ # !\u1|num_clk_s[3]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "5A5F",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[3]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => \u1|num_clk_s[3]\,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => \u1|num_clk_s[2]~172\,
	cin1 => \u1|num_clk_s[2]~172COUT1_253\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[3]~I_modesel\,
	regout => \u1|num_clk_s[3]\,
	cout0 => \u1|num_clk_s[3]~184\,
	cout1 => \u1|num_clk_s[3]~184COUT1_255\);

\u1|num_clk_s[4]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[4]\ = DFFEAS(\u1|num_clk_s[4]\ $ !\u1|num_clk_s[3]~184\, GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[4]~196\ = CARRY(\u1|num_clk_s[4]\ & !\u1|num_clk_s[3]~184COUT1_255\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "C30C",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[4]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => VCC,
	datab => \u1|num_clk_s[4]\,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => GND,
	cin0 => \u1|num_clk_s[3]~184\,
	cin1 => \u1|num_clk_s[3]~184COUT1_255\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[4]~I_modesel\,
	regout => \u1|num_clk_s[4]\,
	cout => \u1|num_clk_s[4]~196\);

\u1|num_clk_s[5]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[5]\ = DFFEAS(\u1|num_clk_s[5]\ $ \u1|num_clk_s[4]~196\, GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[5]~208\ = CARRY(!\u1|num_clk_s[4]~196\ # !\u1|num_clk_s[5]\)
-- \u1|num_clk_s[5]~208COUT1_257\ = CARRY(!\u1|num_clk_s[4]~196\ # !\u1|num_clk_s[5]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "3C3F",
--	cin_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[5]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => VCC,
	datab => \u1|num_clk_s[5]\,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => \u1|num_clk_s[4]~196\,
	cin0 => GND,
	cin1 => VCC,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[5]~I_modesel\,
	regout => \u1|num_clk_s[5]\,
	cout0 => \u1|num_clk_s[5]~208\,
	cout1 => \u1|num_clk_s[5]~208COUT1_257\);

\u1|num_clk_s[6]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[6]\ = DFFEAS(\u1|num_clk_s[6]\ $ !(!\u1|num_clk_s[4]~196\ & \u1|num_clk_s[5]~208\) # (\u1|num_clk_s[4]~196\ & \u1|num_clk_s[5]~208COUT1_257\), GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[6]~216\ = CARRY(\u1|num_clk_s[6]\ & !\u1|num_clk_s[5]~208\)
-- \u1|num_clk_s[6]~216COUT1_259\ = CARRY(\u1|num_clk_s[6]\ & !\u1|num_clk_s[5]~208COUT1_257\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "C30C",
--	cin_used => "true",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[6]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => VCC,
	datab => \u1|num_clk_s[6]\,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => \u1|num_clk_s[4]~196\,
	cin0 => \u1|num_clk_s[5]~208\,
	cin1 => \u1|num_clk_s[5]~208COUT1_257\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[6]~I_modesel\,
	regout => \u1|num_clk_s[6]\,
	cout0 => \u1|num_clk_s[6]~216\,
	cout1 => \u1|num_clk_s[6]~216COUT1_259\);

\u1|num_clk_s[7]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[7]\ = DFFEAS(\u1|num_clk_s[7]\ $ (!\u1|num_clk_s[4]~196\ & \u1|num_clk_s[6]~216\) # (\u1|num_clk_s[4]~196\ & \u1|num_clk_s[6]~216COUT1_259\), GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[7]~224\ = CARRY(!\u1|num_clk_s[6]~216\ # !\u1|num_clk_s[7]\)
-- \u1|num_clk_s[7]~224COUT1_261\ = CARRY(!\u1|num_clk_s[6]~216COUT1_259\ # !\u1|num_clk_s[7]\)

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "3C3F",
--	cin_used => "true",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[7]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => VCC,
	datab => \u1|num_clk_s[7]\,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => \u1|num_clk_s[4]~196\,
	cin0 => \u1|num_clk_s[6]~216\,
	cin1 => \u1|num_clk_s[6]~216COUT1_259\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[7]~I_modesel\,
	regout => \u1|num_clk_s[7]\,
	cout0 => \u1|num_clk_s[7]~224\,
	cout1 => \u1|num_clk_s[7]~224COUT1_261\);

\u1|num_clk_s[8]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[8]\ = DFFEAS(\u1|num_clk_s[8]\ $ (!(!\u1|num_clk_s[4]~196\ & \u1|num_clk_s[7]~224\) # (\u1|num_clk_s[4]~196\ & \u1|num_clk_s[7]~224COUT1_261\)), GLOBAL(\clkin~combout\), !GLOBAL(\u1|once\), , , , , , )
-- \u1|num_clk_s[8]~148\ = CARRY(\u1|num_clk_s[8]\ & (!\u1|num_clk_s[7]~224\))
-- \u1|num_clk_s[8]~148COUT1_263\ = CARRY(\u1|num_clk_s[8]\ & (!\u1|num_clk_s[7]~224COUT1_261\))

-- pragma translate_off
-- GENERIC MAP (
--	operation_mode => "arithmetic",
--	synch_mode => "off",
--	register_cascade_mode => "off",
--	sum_lutc_input => "cin",
--	lut_mask => "A50A",
--	cin_used => "true",
--	cin0_used => "true",
--	cin1_used => "true",
--	output_mode => "reg_only")
-- pragma translate_on
PORT MAP (
	pathsel => \u1|num_clk_s[8]~I_pathsel\,
	enable_asynch_arcs => lcell_ff_enable_asynch_arcs_out,
	clk => \clkin~combout\,
	dataa => \u1|num_clk_s[8]\,
	datab => VCC,
	datac => VCC,
	datad => VCC,
	aclr => \u1|once\,
	aload => GND,
	sclr => GND,
	sload => GND,
	ena => VCC,
	cin => \u1|num_clk_s[4]~196\,
	cin0 => \u1|num_clk_s[7]~224\,
	cin1 => \u1|num_clk_s[7]~224COUT1_261\,
	inverta => GND,
	regcascin => GND,
	modesel => \u1|num_clk_s[8]~I_modesel\,
	regout => \u1|num_clk_s[8]\,
	cout0 => \u1|num_clk_s[8]~148\,
	cout1 => \u1|num_clk_s[8]~148COUT1_263\);

\u1|num_clk_s[9]~I\ : maxii_lcell
-- Equation(s):
-- \u1|num_clk_s[9]\ = DFFEAS(\u1|num_clk_s[9]\ $ ((!\u1|num_clk_s[4]~196\ & \u1|num_clk_s[8]~148\) # (\u1|num_clk_s[4]~196\ & \u1|num_clk_s[8]~148COUT1_263\)), GLOBAL(\clkin~combout\), !GLOBAL(
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