item_new2.vho

对硅微谐振式加速度计的数据采集电路开展研究工作

SIGNAL \u1|num_a_s[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[17]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[17]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a_s[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[18]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[18]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~432_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~432_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \delay[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \delay[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~433_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~433_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~7_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~7_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \int2_v~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \int2_v~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \int1_v~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \int1_v~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \process0~0_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \process0~0_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data[0]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[1]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[2]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[3]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[4]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[5]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[6]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \data[7]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \intermit~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u2|num_clk[3]\ : std_logic;
SIGNAL \u2|num_clk[11]\ : std_logic;
SIGNAL \u1|num_clk[0]\ : std_logic;
SIGNAL \u1|num_clk[8]\ : std_logic;
SIGNAL \u1|num_a[0]\ : std_logic;
SIGNAL \u2|num_clk[12]\ : std_logic;
SIGNAL \u2|num_clk[4]\ : std_logic;
SIGNAL \u1|num_clk[9]\ : std_logic;
SIGNAL \u1|num_clk[1]\ : std_logic;
SIGNAL \u1|num_a[1]\ : std_logic;
SIGNAL \u1|num_clk[18]\ : std_logic;
SIGNAL \u2|num_clk[13]\ : std_logic;
SIGNAL \u2|num_a[2]\ : std_logic;
SIGNAL \u1|num_clk[2]\ : std_logic;
SIGNAL \u1|num_clk[19]\ : std_logic;
SIGNAL \u2|num_clk[14]\ : std_logic;
SIGNAL \u1|num_clk[3]\ : std_logic;
SIGNAL \u2|num_a[3]\ : std_logic;
SIGNAL \u1|num_clk[20]\ : std_logic;
SIGNAL \u2|num_clk[15]\ : std_logic;
SIGNAL \u2|num_a[4]\ : std_logic;
SIGNAL \u1|num_clk[4]\ : std_logic;
SIGNAL \u2|num_clk[0]\ : std_logic;
SIGNAL \u2|num_clk[16]\ : std_logic;
SIGNAL \u1|num_clk[5]\ : std_logic;
SIGNAL \u2|num_a[5]\ : std_logic;
SIGNAL \u2|num_clk[1]\ : std_logic;
SIGNAL \u2|num_clk[17]\ : std_logic;
SIGNAL \u2|num_a[6]\ : std_logic;
SIGNAL \u1|num_clk[6]\ : std_logic;
SIGNAL \u2|num_clk[2]\ : std_logic;
SIGNAL \u2|num_clk[18]\ : std_logic;
SIGNAL \u1|num_clk[7]\ : std_logic;
SIGNAL \u2|num_a[7]\ : std_logic;
SIGNAL \clkin~combout\ : std_logic;
SIGNAL \ain~combout\ : std_logic;
SIGNAL \sel[1]~combout\ : std_logic;
SIGNAL \sel[2]~combout\ : std_logic;
SIGNAL \rtl~431\ : std_logic;
SIGNAL \sel[0]~combout\ : std_logic;
SIGNAL \u1|num_clk_s[0]\ : std_logic;
SIGNAL \u1|num_clk_s[0]~152\ : std_logic;
SIGNAL \u1|num_clk_s[0]~152COUT1_249\ : std_logic;
SIGNAL \u1|num_clk_s[1]\ : std_logic;
SIGNAL \u1|num_clk_s[1]~160\ : std_logic;
SIGNAL \u1|num_clk_s[1]~160COUT1_251\ : std_logic;
SIGNAL \u1|num_clk_s[2]\ : std_logic;
SIGNAL \u1|num_clk_s[2]~172\ : std_logic;
SIGNAL \u1|num_clk_s[2]~172COUT1_253\ : std_logic;
SIGNAL \u1|num_clk_s[3]\ : std_logic;
SIGNAL \u1|num_clk_s[3]~184\ : std_logic;
SIGNAL \u1|num_clk_s[3]~184COUT1_255\ : std_logic;
SIGNAL \u1|num_clk_s[4]\ : std_logic;
SIGNAL \u1|num_clk_s[4]~196\ : std_logic;
SIGNAL \u1|num_clk_s[5]\ : std_logic;
SIGNAL \u1|num_clk_s[5]~208\ : std_logic;
SIGNAL \u1|num_clk_s[5]~208COUT1_257\ : std_logic;
SIGNAL \u1|num_clk_s[6]\ : std_logic;
SIGNAL \u1|num_clk_s[6]~216\ : std_logic;
SIGNAL \u1|num_clk_s[6]~216COUT1_259\ : std_logic;
SIGNAL \u1|num_clk_s[7]\ : std_logic;
SIGNAL \u1|num_clk_s[7]~224\ : std_logic;
SIGNAL \u1|num_clk_s[7]~224COUT1_261\ : std_logic;
SIGNAL \u1|num_clk_s[8]\ : std_logic;
SIGNAL \u1|num_clk_s[8]~148\ : std_logic;
SIGNAL \u1|num_clk_s[8]~148COUT1_263\ : std_logic;
SIGNAL \u1|num_clk_s[9]\ : std_logic;
SIGNAL \u1|num_clk_s[9]~164\ : std_logic;
SIGNAL \u1|num_clk_s[10]\ : std_logic;
SIGNAL \u1|num_clk_s[10]~180\ : std_logic;
SIGNAL \u1|num_clk_s[10]~180COUT1_265\ : std_logic;
SIGNAL \u1|num_clk_s[11]\ : std_logic;
SIGNAL \u1|num_clk_s[11]~192\ : std_logic;
SIGNAL \u1|num_clk_s[11]~192COUT1_267\ : std_logic;
SIGNAL \u1|num_clk_s[12]\ : std_logic;
SIGNAL \u1|num_clk_s[12]~204\ : std_logic;
SIGNAL \u1|num_clk_s[12]~204COUT1_269\ : std_logic;
SIGNAL \u1|num_clk_s[13]\ : std_logic;
SIGNAL \u1|num_clk_s[13]~212\ : std_logic;
SIGNAL \u1|num_clk_s[13]~212COUT1_271\ : std_logic;
SIGNAL \u1|num_clk_s[14]\ : std_logic;
SIGNAL \rtl~439\ : std_logic;
SIGNAL \u1|num_clk_s[14]~220\ : std_logic;
SIGNAL \u1|num_clk_s[15]\ : std_logic;
SIGNAL \u1|num_clk_s[15]~228\ : std_logic;
SIGNAL \u1|num_clk_s[15]~228COUT1_273\ : std_logic;
SIGNAL \u1|num_clk_s[16]\ : std_logic;
SIGNAL \rtl~434\ : std_logic;
SIGNAL \u1|num_clk_s[16]~156\ : std_logic;
SIGNAL \u1|num_clk_s[16]~156COUT1_275\ : std_logic;
SIGNAL \u1|num_clk_s[17]\ : std_logic;
SIGNAL \u1|num_clk_s[17]~168\ : std_logic;
SIGNAL \u1|num_clk_s[17]~168COUT1_277\ : std_logic;
SIGNAL \u1|num_clk_s[18]\ : std_logic;
SIGNAL \rtl~435\ : std_logic;
SIGNAL \u1|num_clk_s[18]~176\ : std_logic;
SIGNAL \u1|num_clk_s[18]~176COUT1_279\ : std_logic;
SIGNAL \u1|num_clk_s[19]\ : std_logic;
SIGNAL \u1|num_clk_s[19]~188\ : std_logic;
SIGNAL \u1|num_clk_s[20]\ : std_logic;
SIGNAL \rtl~437\ : std_logic;
SIGNAL \rtl~436\ : std_logic;
SIGNAL \rtl~438\ : std_logic;
SIGNAL \rtl~8\ : std_logic;
SIGNAL \u1|p_b:lastone\ : std_logic;
SIGNAL \u1|once\ : std_logic;
SIGNAL \u1|num_a_s[0]\ : std_logic;
SIGNAL \u2|num_clk_s[0]\ : std_logic;
SIGNAL \u2|num_clk_s[0]~204\ : std_logic;
SIGNAL \u2|num_clk_s[0]~204COUT1_249\ : std_logic;
SIGNAL \u2|num_clk_s[1]\ : std_logic;
SIGNAL \u2|num_clk_s[1]~216\ : std_logic;
SIGNAL \u2|num_clk_s[1]~216COUT1_251\ : std_logic;
SIGNAL \u2|num_clk_s[2]\ : std_logic;
SIGNAL \u2|num_clk_s[2]~228\ : std_logic;
SIGNAL \u2|num_clk_s[2]~228COUT1_253\ : std_logic;
SIGNAL \u2|num_clk_s[3]\ : std_logic;
SIGNAL \u2|num_clk_s[3]~152\ : std_logic;
SIGNAL \u2|num_clk_s[3]~152COUT1_255\ : std_logic;
SIGNAL \u2|num_clk_s[4]\ : std_logic;
SIGNAL \u2|num_clk_s[4]~160\ : std_logic;
SIGNAL \u2|num_clk_s[5]\ : std_logic;
SIGNAL \u2|num_clk_s[5]~176\ : std_logic;
SIGNAL \u2|num_clk_s[5]~176COUT1_257\ : std_logic;
SIGNAL \u2|num_clk_s[6]\ : std_logic;
SIGNAL \u2|num_clk_s[6]~184\ : std_logic;
SIGNAL \u2|num_clk_s[6]~184COUT1_259\ : std_logic;
SIGNAL \u2|num_clk_s[7]\ : std_logic;
SIGNAL \u2|num_clk_s[7]~192\ : std_logic;
SIGNAL \u2|num_clk_s[7]~192COUT1_261\ : std_logic;
SIGNAL \u2|num_clk_s[8]\ : std_logic;
SIGNAL \u2|num_clk_s[8]~200\ : std_logic;
SIGNAL \u2|num_clk_s[8]~200COUT1_263\ : std_logic;
SIGNAL \u2|num_clk_s[9]\ : std_logic;
SIGNAL \u2|num_clk_s[9]~212\ : std_logic;
SIGNAL \u2|num_clk_s[10]\ : std_logic;
SIGNAL \u2|num_clk_s[10]~224\ : std_logic;
SIGNAL \u2|num_clk_s[10]~224COUT1_265\ : std_logic;
SIGNAL \u2|num_clk_s[11]\ : std_logic;
SIGNAL \u2|num_clk_s[11]~148\ : std_logic;
SIGNAL \u2|num_clk_s[11]~148COUT1_267\ : std_logic;
SIGNAL \u2|num_clk_s[12]\ : std_logic;
SIGNAL \u2|num_clk_s[12]~164\ : std_logic;
SIGNAL \u2|num_clk_s[12]~164COUT1_269\ : std_logic;
SIGNAL \u2|num_clk_s[13]\ : std_logic;
SIGNAL \u2|num_clk_s[13]~172\ : std_logic;
SIGNAL \u2|num_clk_s[13]~172COUT1_271\ : std_logic;
SIGNAL \u2|num_clk_s[14]\ : std_logic;
SIGNAL \u2|num_clk_s[14]~180\ : std_logic;
SIGNAL \u2|num_clk_s[15]\ : std_logic;
SIGNAL \u2|num_clk_s[15]~188\ : std_logic;
SIGNAL \u2|num_clk_s[15]~188COUT1_273\ : std_logic;
SIGNAL \u2|num_clk_s[16]\ : std_logic;
SIGNAL \u2|num_clk_s[16]~196\ : std_logic;
SIGNAL \u2|num_clk_s[16]~196COUT1_275\ : std_logic;
SIGNAL \u2|num_clk_s[17]\ : std_logic;
SIGNAL \u2|num_clk_s[17]~208\ : std_logic;
SIGNAL \u2|num_clk_s[17]~208COUT1_277\ : std_logic;
SIGNAL \u2|num_clk_s[18]\ : std_logic;
SIGNAL \rtl~445\ : std_logic;
SIGNAL \u2|num_clk_s[18]~220\ : std_logic;
SIGNAL \u2|num_clk_s[18]~220COUT1_279\ : std_logic;
SIGNAL \u2|num_clk_s[19]\ : std_logic;
SIGNAL \u2|num_clk_s[19]~156\ : std_logic;
SIGNAL \u2|num_clk_s[20]\ : std_logic;
SIGNAL \rtl~441\ : std_logic;
SIGNAL \rtl~442\ : std_logic;
SIGNAL \rtl~440\ : std_logic;
SIGNAL \rtl~443\ : std_logic;
SIGNAL \rtl~444\ : std_logic;
SIGNAL \rtl~9\ : std_logic;
SIGNAL \u2|p_b:lastone\ : std_logic;
SIGNAL \u2|once\ : std_logic;
SIGNAL \u2|num_a_s[0]\ : std_logic;
SIGNAL \u2|num_a[0]\ : std_logic;
SIGNAL \rtl~429\ : std_logic;
SIGNAL \data~541\ : std_logic;
SIGNAL \data~542\ : std_logic;
SIGNAL \u1|num_clk[16]\ : std_logic;
SIGNAL \rtl~430\ : std_logic;
SIGNAL \u2|num_clk[19]\ : std_logic;
SIGNAL \data~543\ : std_logic;
SIGNAL \data~544\ : std_logic;
SIGNAL \data~545\ : std_logic;
SIGNAL \data~546\ : std_logic;
SIGNAL \data~547\ : std_logic;
SIGNAL \~GND\ : std_logic;
SIGNAL \u1|num_a_s[0]~57\ : std_logic;
SIGNAL \u1|num_a_s[0]~57COUT1_95\ : std_logic;
SIGNAL \u1|num_a_s[1]\ : std_logic;
SIGNAL \u2|num_a_s[0]~57\ : std_logic;
SIGNAL \u2|num_a_s[0]~57COUT1_95\ : std_logic;
SIGNAL \u2|num_a_s[1]\ : std_logic;
SIGNAL \u2|num_a[1]\ : std_logic;
SIGNAL \u1|num_clk[17]\ : std_logic;
SIGNAL \u2|num_clk[20]\ : std_logic;
SIGNAL \data~548\ : std_logic;
SIGNAL \data~549\ : std_logic;
SIGNAL \data~550\ : std_logic;
SIGNAL \data~551\ : std_logic;
SIGNAL \data~552\ : std_logic;
SIGNAL \u1|num_a_s[1]~61\ : std_logic;
SIGNAL \u1|num_a_s[1]~61COUT1_97\ : std_logic;
SIGNAL \u1|num_a_s[2]\ : std_logic;
SIGNAL \u1|num_a[2]\ : std_logic;
SIGNAL \data~553\ : std_logic;
SIGNAL \u2|num_a_s[1]~61\ : std_logic;
SIGNAL \u2|num_a_s[1]~61COUT1_97\ : std_logic;
SIGNAL \u2|num_a_s[2]\ : std_logic;
SIGNAL \u2|num_clk[5]\ : std_logic;
SIGNAL \data~554\ : std_logic;
SIGNAL \data~555\ : std_logic;
SIGNAL \data~556\ : std_logic;
SIGNAL \u1|num_clk[10]\ : std_logic;
SIGNAL \data~557\ : std_logic;
SIGNAL \data~558\ : std_logic;
SIGNAL \data~559\ : std_logic;
SIGNAL \data~560\ : std_logic;
SIGNAL \bin~combout\ : std_logic;
SIGNAL \u1|num_a_s[2]~65\ : std_logic;
SIGNAL \u1|num_a_s[2]~65COUT1_99\ : std_logic;
SIGNAL \u1|num_a_s[3]\ : std_logic;
SIGNAL \u1|num_a[3]\ : std_logic;
SIGNAL \u2|num_a_s[2]~65\ : std_logic;
SIGNAL \u2|num_a_s[2]~65COUT1_99\ : std_logic;
SIGNAL \u2|num_a_s[3]\ : std_logic;
SIGNAL \u2|num_clk[6]\ : std_logic;
SIGNAL \u1|num_clk[11]\ : std_logic;
SIGNAL \data~561\ : std_logic;
SIGNAL \data~562\ : std_logic;
SIGNAL \data~563\ : std_logic;
SIGNAL \data~564\ : std_logic;
SIGNAL \u1|num_a_s[3]~69\ : std_logic;
SIGNAL \u1|num_a_s[3]~69COUT1_100\ : std_logic;
SIGNAL \u1|num_a_s[4]\ : std_logic;
SIGNAL \u1|num_a[4]\ : std_logic;
SIGNAL \u2|num_a_s[3]~69\ : std_logic;
SIGNAL \u2|num_a_s[3]~69COUT1_100\ : std_logic;
SIGNAL \u2|num_a_s[4]\ : std_logic;