item_new2.vho

对硅微谐振式加速度计的数据采集电路开展研究工作

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Web Edition"

-- DATE "08/22/2008 14:34:38"

-- 
-- Device: Altera EPM240T100C5 Package TQFP100
-- 

-- 
-- This VHDL file should be used for PRIMETIME only
-- 

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;

ENTITY 	item_new2 IS
    PORT (
	ain : IN std_logic;
	bin : IN std_logic;
	clkin : IN std_logic;
	sel : IN std_logic_vector(2 DOWNTO 0);
	data : OUT std_logic_vector(7 DOWNTO 0);
	intermit : OUT std_logic
	);
END item_new2;

ARCHITECTURE structure OF item_new2 IS
SIGNAL GNDs : std_logic_vector(1024 DOWNTO 0);
SIGNAL VCCs : std_logic_vector(1024 DOWNTO 0);
SIGNAL gnd : std_logic;
SIGNAL vcc : std_logic;
SIGNAL lcell_ff_enable_asynch_arcs_out : std_logic;
SIGNAL ww_ain : std_logic;
SIGNAL ww_bin : std_logic;
SIGNAL ww_clkin : std_logic;
SIGNAL ww_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_data : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_intermit : std_logic;
SIGNAL \clkin~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \ain~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \sel[1]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \sel[2]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \rtl~431_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~431_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \sel[0]~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u1|num_clk_s[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~439_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~439_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~434_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~434_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[17]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[17]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[18]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[18]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~435_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~435_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[19]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[19]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk_s[20]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk_s[20]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~437_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~437_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~436_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~436_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~438_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~438_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~8_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~8_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|p_b:lastone~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|p_b:lastone~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|once~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|once~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a_s[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[17]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[17]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[18]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[18]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~445_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~445_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[19]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[19]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk_s[20]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk_s[20]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~441_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~441_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~442_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~442_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~440_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~440_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~443_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~443_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~444_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~444_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~9_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~9_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|p_b:lastone~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|p_b:lastone~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|once~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|once~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~429_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~429_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data~541_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \data~541_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data~542_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \data~542_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \rtl~430_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \rtl~430_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[19]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[19]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \~GND~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \~GND~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a_s[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[17]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[17]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[20]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[20]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[9]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[9]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[1]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[1]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a_s[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data~553_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \data~553_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data~554_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \data~554_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data~555_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \data~555_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \data~556_I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \data~556_I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[10]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[10]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[18]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[18]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[2]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[2]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \bin~I_modesel\ : std_logic_vector(7 DOWNTO 0);
SIGNAL \u1|num_a_s[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[6]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[6]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[11]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[11]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[19]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[19]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[14]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[14]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[3]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[3]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a_s[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[7]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[7]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[12]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[12]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[20]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[20]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[15]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[15]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[4]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[4]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a_s[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a_s[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_a[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_a[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a_s[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a_s[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[8]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[8]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[13]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[13]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[0]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[0]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_clk[16]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_clk[16]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u1|num_clk[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u1|num_clk[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);
SIGNAL \u2|num_a[5]~I_modesel\ : std_logic_vector(12 DOWNTO 0);
SIGNAL \u2|num_a[5]~I_pathsel\ : std_logic_vector(10 DOWNTO 0);