itemnew3_2.eda.rpt

对硅微谐振式加速度计的数据采集电路开展研究工作

EDA Netlist Writer report for itemnew3_2
Tue Aug 19 10:25:40 2008
Version 5.1 Build 176 10/26/2005 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Tool Settings
  4. Simulation Tool Generated Files
  5. Timing Analysis Tool Settings
  6. Timing Analysis Tool Generated Files
  7. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; EDA Netlist Writer Summary                                          ;
+-----------------------------+---------------------------------------+
; EDA Netlist Writer Status   ; Successful - Tue Aug 19 10:25:40 2008 ;
; Revision Name               ; itemnew3_2                            ;
; Top-level Entity Name       ; itemnew3_2                            ;
; Family                      ; MAX II                                ;
; Simulation Tool Writer      ; Successful                            ;
; Timing Analysis Tool Writer ; Successful                            ;
+-----------------------------+---------------------------------------+


+------------------------------------------------------------------------+
; Simulation Tool Settings                                               ;
+------------------------------------------------------+-----------------+
; Option                                               ; Setting         ;
+------------------------------------------------------+-----------------+
; Tool Name                                            ; ModelSim (VHDL) ;
; Generate Netlist for Functional Simulation Only      ; Off             ;
; Time scale                                           ; 1 ps            ;
; Truncate long hierarchy paths                        ; Off             ;
; Map illegal HDL characters                           ; Off             ;
; Flatten buses into individual nodes                  ; Off             ;
; Maintain hierarchy                                   ; Off             ;
; Bring out device-wide set/reset signals as ports     ; Off             ;
; Output Excalibur stripe as a single module or entity ; Off             ;
; Enable glitch filtering                              ; Off             ;
+------------------------------------------------------+-----------------+


+-----------------------------------------------------+
; Simulation Tool Generated Files                     ;
+-----------------------------------------------------+
; Generated Files                                     ;
+-----------------------------------------------------+
; F:/quartus51/simulation/modelsim/itemnew3_2.vho     ;
; F:/quartus51/simulation/modelsim/itemnew3_2_vhd.sdo ;
+-----------------------------------------------------+


+-------------------------------------------------------------------------+
; Timing Analysis Tool Settings                                           ;
+------------------------------------------------------+------------------+
; Option                                               ; Setting          ;
+------------------------------------------------------+------------------+
; Tool Name                                            ; PrimeTime (VHDL) ;
; Time scale                                           ; 1 ps             ;
; Truncate long hierarchy paths                        ; Off              ;
; Map illegal HDL characters                           ; Off              ;
; Flatten buses into individual nodes                  ; Off              ;
; Output Excalibur stripe as a single module or entity ; Off              ;
+------------------------------------------------------+------------------+


+-----------------------------------------------------+
; Timing Analysis Tool Generated Files                ;
+-----------------------------------------------------+
; Generated Files                                     ;
+-----------------------------------------------------+
; F:/quartus51/timing/primetime/itemnew3_2.vho        ;
; F:/quartus51/timing/primetime/itemnew3_2_vhd.sdo    ;
; F:/quartus51/timing/primetime/itemnew3_2_pt_vhd.tcl ;
+-----------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition
    Info: Processing started: Tue Aug 19 10:25:39 2008
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off itemnew3_2 -c itemnew3_2
Info: Generated files "itemnew3_2.vho" and "itemnew3_2_vhd.sdo" in directory "F:/quartus51/simulation/modelsim/" for EDA simulation tool
Info: Generated files "itemnew3_2.vho" and "itemnew3_2_vhd.sdo" in directory "F:/quartus51/timing/primetime/" for EDA timing analysis tool
Info: Generated PrimeTime Tcl script file timing/primetime/itemnew3_2_pt_vhd.tcl
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Tue Aug 19 10:25:40 2008
    Info: Elapsed time: 00:00:02