item_new2.vho

对硅微谐振式加速度计的数据采集电路开展研究工作

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- VENDOR "Altera"
-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Web Edition"

-- DATE "08/22/2008 14:34:38"

-- 
-- Device: Altera EPM240T100C5 Package TQFP100
-- 

-- 
-- This VHDL file should be used for ModelSim (VHDL) only
-- 

LIBRARY IEEE, maxii;
USE IEEE.std_logic_1164.all;
USE maxii.maxii_components.all;

ENTITY 	item_new2 IS
    PORT (
	ain : IN std_logic;
	bin : IN std_logic;
	clkin : IN std_logic;
	sel : IN std_logic_vector(2 DOWNTO 0);
	data : OUT std_logic_vector(7 DOWNTO 0);
	intermit : OUT std_logic
	);
END item_new2;

ARCHITECTURE structure OF item_new2 IS
SIGNAL gnd : std_logic := '0';
SIGNAL vcc : std_logic := '1';
SIGNAL devoe : std_logic := '0';
SIGNAL devclrn : std_logic := '1';
SIGNAL devpor : std_logic := '1';
SIGNAL ww_devoe : std_logic;
SIGNAL ww_devclrn : std_logic;
SIGNAL ww_devpor : std_logic;
SIGNAL ww_ain : std_logic;
SIGNAL ww_bin : std_logic;
SIGNAL ww_clkin : std_logic;
SIGNAL ww_sel : std_logic_vector(2 DOWNTO 0);
SIGNAL ww_data : std_logic_vector(7 DOWNTO 0);
SIGNAL ww_intermit : std_logic;
SIGNAL \u2|num_clk[3]\ : std_logic;
SIGNAL \u2|num_clk[11]\ : std_logic;
SIGNAL \u1|num_clk[0]\ : std_logic;
SIGNAL \u1|num_clk[8]\ : std_logic;
SIGNAL \u1|num_a[0]\ : std_logic;
SIGNAL \u2|num_clk[12]\ : std_logic;
SIGNAL \u2|num_clk[4]\ : std_logic;
SIGNAL \u1|num_clk[9]\ : std_logic;
SIGNAL \u1|num_clk[1]\ : std_logic;
SIGNAL \u1|num_a[1]\ : std_logic;
SIGNAL \u1|num_clk[18]\ : std_logic;
SIGNAL \u2|num_clk[13]\ : std_logic;
SIGNAL \u2|num_a[2]\ : std_logic;
SIGNAL \u1|num_clk[2]\ : std_logic;
SIGNAL \u1|num_clk[19]\ : std_logic;
SIGNAL \u2|num_clk[14]\ : std_logic;
SIGNAL \u1|num_clk[3]\ : std_logic;
SIGNAL \u2|num_a[3]\ : std_logic;
SIGNAL \u1|num_clk[20]\ : std_logic;
SIGNAL \u2|num_clk[15]\ : std_logic;
SIGNAL \u2|num_a[4]\ : std_logic;
SIGNAL \u1|num_clk[4]\ : std_logic;
SIGNAL \u2|num_clk[0]\ : std_logic;
SIGNAL \u2|num_clk[16]\ : std_logic;
SIGNAL \u1|num_clk[5]\ : std_logic;
SIGNAL \u2|num_a[5]\ : std_logic;
SIGNAL \u2|num_clk[1]\ : std_logic;
SIGNAL \u2|num_clk[17]\ : std_logic;
SIGNAL \u2|num_a[6]\ : std_logic;
SIGNAL \u1|num_clk[6]\ : std_logic;
SIGNAL \u2|num_clk[2]\ : std_logic;
SIGNAL \u2|num_clk[18]\ : std_logic;
SIGNAL \u1|num_clk[7]\ : std_logic;
SIGNAL \u2|num_a[7]\ : std_logic;
SIGNAL \clkin~combout\ : std_logic;
SIGNAL \ain~combout\ : std_logic;
SIGNAL \sel[1]~combout\ : std_logic;
SIGNAL \sel[2]~combout\ : std_logic;
SIGNAL \rtl~431\ : std_logic;
SIGNAL \sel[0]~combout\ : std_logic;
SIGNAL \u1|num_clk_s[0]\ : std_logic;
SIGNAL \u1|num_clk_s[0]~152\ : std_logic;
SIGNAL \u1|num_clk_s[0]~152COUT1_249\ : std_logic;
SIGNAL \u1|num_clk_s[1]\ : std_logic;
SIGNAL \u1|num_clk_s[1]~160\ : std_logic;
SIGNAL \u1|num_clk_s[1]~160COUT1_251\ : std_logic;
SIGNAL \u1|num_clk_s[2]\ : std_logic;
SIGNAL \u1|num_clk_s[2]~172\ : std_logic;
SIGNAL \u1|num_clk_s[2]~172COUT1_253\ : std_logic;
SIGNAL \u1|num_clk_s[3]\ : std_logic;
SIGNAL \u1|num_clk_s[3]~184\ : std_logic;
SIGNAL \u1|num_clk_s[3]~184COUT1_255\ : std_logic;
SIGNAL \u1|num_clk_s[4]\ : std_logic;
SIGNAL \u1|num_clk_s[4]~196\ : std_logic;
SIGNAL \u1|num_clk_s[5]\ : std_logic;
SIGNAL \u1|num_clk_s[5]~208\ : std_logic;
SIGNAL \u1|num_clk_s[5]~208COUT1_257\ : std_logic;
SIGNAL \u1|num_clk_s[6]\ : std_logic;
SIGNAL \u1|num_clk_s[6]~216\ : std_logic;
SIGNAL \u1|num_clk_s[6]~216COUT1_259\ : std_logic;
SIGNAL \u1|num_clk_s[7]\ : std_logic;
SIGNAL \u1|num_clk_s[7]~224\ : std_logic;
SIGNAL \u1|num_clk_s[7]~224COUT1_261\ : std_logic;
SIGNAL \u1|num_clk_s[8]\ : std_logic;
SIGNAL \u1|num_clk_s[8]~148\ : std_logic;
SIGNAL \u1|num_clk_s[8]~148COUT1_263\ : std_logic;
SIGNAL \u1|num_clk_s[9]\ : std_logic;
SIGNAL \u1|num_clk_s[9]~164\ : std_logic;
SIGNAL \u1|num_clk_s[10]\ : std_logic;
SIGNAL \u1|num_clk_s[10]~180\ : std_logic;
SIGNAL \u1|num_clk_s[10]~180COUT1_265\ : std_logic;
SIGNAL \u1|num_clk_s[11]\ : std_logic;
SIGNAL \u1|num_clk_s[11]~192\ : std_logic;
SIGNAL \u1|num_clk_s[11]~192COUT1_267\ : std_logic;
SIGNAL \u1|num_clk_s[12]\ : std_logic;
SIGNAL \u1|num_clk_s[12]~204\ : std_logic;
SIGNAL \u1|num_clk_s[12]~204COUT1_269\ : std_logic;
SIGNAL \u1|num_clk_s[13]\ : std_logic;
SIGNAL \u1|num_clk_s[13]~212\ : std_logic;
SIGNAL \u1|num_clk_s[13]~212COUT1_271\ : std_logic;
SIGNAL \u1|num_clk_s[14]\ : std_logic;
SIGNAL \rtl~439\ : std_logic;
SIGNAL \u1|num_clk_s[14]~220\ : std_logic;
SIGNAL \u1|num_clk_s[15]\ : std_logic;
SIGNAL \u1|num_clk_s[15]~228\ : std_logic;
SIGNAL \u1|num_clk_s[15]~228COUT1_273\ : std_logic;
SIGNAL \u1|num_clk_s[16]\ : std_logic;
SIGNAL \rtl~434\ : std_logic;
SIGNAL \u1|num_clk_s[16]~156\ : std_logic;
SIGNAL \u1|num_clk_s[16]~156COUT1_275\ : std_logic;
SIGNAL \u1|num_clk_s[17]\ : std_logic;
SIGNAL \u1|num_clk_s[17]~168\ : std_logic;
SIGNAL \u1|num_clk_s[17]~168COUT1_277\ : std_logic;
SIGNAL \u1|num_clk_s[18]\ : std_logic;
SIGNAL \rtl~435\ : std_logic;
SIGNAL \u1|num_clk_s[18]~176\ : std_logic;
SIGNAL \u1|num_clk_s[18]~176COUT1_279\ : std_logic;
SIGNAL \u1|num_clk_s[19]\ : std_logic;
SIGNAL \u1|num_clk_s[19]~188\ : std_logic;
SIGNAL \u1|num_clk_s[20]\ : std_logic;
SIGNAL \rtl~437\ : std_logic;
SIGNAL \rtl~436\ : std_logic;
SIGNAL \rtl~438\ : std_logic;
SIGNAL \rtl~8\ : std_logic;
SIGNAL \u1|p_b:lastone\ : std_logic;
SIGNAL \u1|once\ : std_logic;
SIGNAL \u1|num_a_s[0]\ : std_logic;
SIGNAL \u2|num_clk_s[0]\ : std_logic;
SIGNAL \u2|num_clk_s[0]~204\ : std_logic;
SIGNAL \u2|num_clk_s[0]~204COUT1_249\ : std_logic;
SIGNAL \u2|num_clk_s[1]\ : std_logic;
SIGNAL \u2|num_clk_s[1]~216\ : std_logic;
SIGNAL \u2|num_clk_s[1]~216COUT1_251\ : std_logic;
SIGNAL \u2|num_clk_s[2]\ : std_logic;
SIGNAL \u2|num_clk_s[2]~228\ : std_logic;
SIGNAL \u2|num_clk_s[2]~228COUT1_253\ : std_logic;
SIGNAL \u2|num_clk_s[3]\ : std_logic;
SIGNAL \u2|num_clk_s[3]~152\ : std_logic;
SIGNAL \u2|num_clk_s[3]~152COUT1_255\ : std_logic;
SIGNAL \u2|num_clk_s[4]\ : std_logic;
SIGNAL \u2|num_clk_s[4]~160\ : std_logic;
SIGNAL \u2|num_clk_s[5]\ : std_logic;
SIGNAL \u2|num_clk_s[5]~176\ : std_logic;
SIGNAL \u2|num_clk_s[5]~176COUT1_257\ : std_logic;
SIGNAL \u2|num_clk_s[6]\ : std_logic;
SIGNAL \u2|num_clk_s[6]~184\ : std_logic;
SIGNAL \u2|num_clk_s[6]~184COUT1_259\ : std_logic;
SIGNAL \u2|num_clk_s[7]\ : std_logic;
SIGNAL \u2|num_clk_s[7]~192\ : std_logic;
SIGNAL \u2|num_clk_s[7]~192COUT1_261\ : std_logic;
SIGNAL \u2|num_clk_s[8]\ : std_logic;
SIGNAL \u2|num_clk_s[8]~200\ : std_logic;
SIGNAL \u2|num_clk_s[8]~200COUT1_263\ : std_logic;
SIGNAL \u2|num_clk_s[9]\ : std_logic;
SIGNAL \u2|num_clk_s[9]~212\ : std_logic;
SIGNAL \u2|num_clk_s[10]\ : std_logic;
SIGNAL \u2|num_clk_s[10]~224\ : std_logic;
SIGNAL \u2|num_clk_s[10]~224COUT1_265\ : std_logic;
SIGNAL \u2|num_clk_s[11]\ : std_logic;
SIGNAL \u2|num_clk_s[11]~148\ : std_logic;
SIGNAL \u2|num_clk_s[11]~148COUT1_267\ : std_logic;
SIGNAL \u2|num_clk_s[12]\ : std_logic;
SIGNAL \u2|num_clk_s[12]~164\ : std_logic;
SIGNAL \u2|num_clk_s[12]~164COUT1_269\ : std_logic;
SIGNAL \u2|num_clk_s[13]\ : std_logic;
SIGNAL \u2|num_clk_s[13]~172\ : std_logic;
SIGNAL \u2|num_clk_s[13]~172COUT1_271\ : std_logic;
SIGNAL \u2|num_clk_s[14]\ : std_logic;
SIGNAL \u2|num_clk_s[14]~180\ : std_logic;
SIGNAL \u2|num_clk_s[15]\ : std_logic;
SIGNAL \u2|num_clk_s[15]~188\ : std_logic;
SIGNAL \u2|num_clk_s[15]~188COUT1_273\ : std_logic;
SIGNAL \u2|num_clk_s[16]\ : std_logic;
SIGNAL \u2|num_clk_s[16]~196\ : std_logic;
SIGNAL \u2|num_clk_s[16]~196COUT1_275\ : std_logic;
SIGNAL \u2|num_clk_s[17]\ : std_logic;
SIGNAL \u2|num_clk_s[17]~208\ : std_logic;
SIGNAL \u2|num_clk_s[17]~208COUT1_277\ : std_logic;
SIGNAL \u2|num_clk_s[18]\ : std_logic;
SIGNAL \rtl~445\ : std_logic;
SIGNAL \u2|num_clk_s[18]~220\ : std_logic;
SIGNAL \u2|num_clk_s[18]~220COUT1_279\ : std_logic;
SIGNAL \u2|num_clk_s[19]\ : std_logic;
SIGNAL \u2|num_clk_s[19]~156\ : std_logic;
SIGNAL \u2|num_clk_s[20]\ : std_logic;
SIGNAL \rtl~441\ : std_logic;
SIGNAL \rtl~442\ : std_logic;
SIGNAL \rtl~440\ : std_logic;
SIGNAL \rtl~443\ : std_logic;
SIGNAL \rtl~444\ : std_logic;
SIGNAL \rtl~9\ : std_logic;
SIGNAL \u2|p_b:lastone\ : std_logic;
SIGNAL \u2|once\ : std_logic;
SIGNAL \u2|num_a_s[0]\ : std_logic;
SIGNAL \u2|num_a[0]\ : std_logic;
SIGNAL \rtl~429\ : std_logic;
SIGNAL \data~541\ : std_logic;
SIGNAL \data~542\ : std_logic;
SIGNAL \u1|num_clk[16]\ : std_logic;
SIGNAL \rtl~430\ : std_logic;
SIGNAL \u2|num_clk[19]\ : std_logic;
SIGNAL \data~543\ : std_logic;
SIGNAL \data~544\ : std_logic;
SIGNAL \data~545\ : std_logic;
SIGNAL \data~546\ : std_logic;
SIGNAL \data~547\ : std_logic;
SIGNAL \~GND\ : std_logic;
SIGNAL \u1|num_a_s[0]~57\ : std_logic;
SIGNAL \u1|num_a_s[0]~57COUT1_95\ : std_logic;
SIGNAL \u1|num_a_s[1]\ : std_logic;
SIGNAL \u2|num_a_s[0]~57\ : std_logic;
SIGNAL \u2|num_a_s[0]~57COUT1_95\ : std_logic;
SIGNAL \u2|num_a_s[1]\ : std_logic;
SIGNAL \u2|num_a[1]\ : std_logic;
SIGNAL \u1|num_clk[17]\ : std_logic;
SIGNAL \u2|num_clk[20]\ : std_logic;
SIGNAL \data~548\ : std_logic;
SIGNAL \data~549\ : std_logic;
SIGNAL \data~550\ : std_logic;
SIGNAL \data~551\ : std_logic;
SIGNAL \data~552\ : std_logic;
SIGNAL \u1|num_a_s[1]~61\ : std_logic;
SIGNAL \u1|num_a_s[1]~61COUT1_97\ : std_logic;
SIGNAL \u1|num_a_s[2]\ : std_logic;
SIGNAL \u1|num_a[2]\ : std_logic;
SIGNAL \data~553\ : std_logic;
SIGNAL \u2|num_a_s[1]~61\ : std_logic;
SIGNAL \u2|num_a_s[1]~61COUT1_97\ : std_logic;
SIGNAL \u2|num_a_s[2]\ : std_logic;
SIGNAL \u2|num_clk[5]\ : std_logic;
SIGNAL \data~554\ : std_logic;
SIGNAL \data~555\ : std_logic;
SIGNAL \data~556\ : std_logic;
SIGNAL \u1|num_clk[10]\ : std_logic;
SIGNAL \data~557\ : std_logic;
SIGNAL \data~558\ : std_logic;
SIGNAL \data~559\ : std_logic;
SIGNAL \data~560\ : std_logic;
SIGNAL \bin~combout\ : std_logic;
SIGNAL \u1|num_a_s[2]~65\ : std_logic;
SIGNAL \u1|num_a_s[2]~65COUT1_99\ : std_logic;
SIGNAL \u1|num_a_s[3]\ : std_logic;
SIGNAL \u1|num_a[3]\ : std_logic;
SIGNAL \u2|num_a_s[2]~65\ : std_logic;
SIGNAL \u2|num_a_s[2]~65COUT1_99\ : std_logic;
SIGNAL \u2|num_a_s[3]\ : std_logic;
SIGNAL \u2|num_clk[6]\ : std_logic;
SIGNAL \u1|num_clk[11]\ : std_logic;
SIGNAL \data~561\ : std_logic;
SIGNAL \data~562\ : std_logic;
SIGNAL \data~563\ : std_logic;
SIGNAL \data~564\ : std_logic;
SIGNAL \u1|num_a_s[3]~69\ : std_logic;
SIGNAL \u1|num_a_s[3]~69COUT1_100\ : std_logic;
SIGNAL \u1|num_a_s[4]\ : std_logic;
SIGNAL \u1|num_a[4]\ : std_logic;
SIGNAL \u2|num_a_s[3]~69\ : std_logic;
SIGNAL \u2|num_a_s[3]~69COUT1_100\ : std_logic;
SIGNAL \u2|num_a_s[4]\ : std_logic;
SIGNAL \u2|num_clk[7]\ : std_logic;
SIGNAL \u1|num_clk[12]\ : std_logic;
SIGNAL \data~565\ : std_logic;
SIGNAL \data~566\ : std_logic;
SIGNAL \data~567\ : std_logic;
SIGNAL \data~568\ : std_logic;
SIGNAL \u1|num_a_s[4]~73\ : std_logic;
SIGNAL \u1|num_a_s[5]\ : std_logic;
SIGNAL \u1|num_a[5]\ : std_logic;
SIGNAL \u2|num_a_s[4]~73\ : std_logic;
SIGNAL \u2|num_a_s[5]\ : std_logic;
SIGNAL \u2|num_clk[8]\ : std_logic;
SIGNAL \u1|num_clk[13]\ : std_logic;
SIGNAL \data~569\ : std_logic;
SIGNAL \data~570\ : std_logic;
SIGNAL \data~571\ : std_logic;
SIGNAL \data~572\ : std_logic;
SIGNAL \u1|num_a_s[5]~77\ : std_logic;
SIGNAL \u1|num_a_s[5]~77COUT1_102\ : std_logic;
SIGNAL \u1|num_a_s[6]\ : std_logic;
SIGNAL \u1|num_a[6]\ : std_logic;
SIGNAL \u2|num_a_s[5]~77\ : std_logic;
SIGNAL \u2|num_a_s[5]~77COUT1_102\ : std_logic;
SIGNAL \u2|num_a_s[6]\ : std_logic;
SIGNAL \u2|num_clk[9]\ : std_logic;
SIGNAL \u1|num_clk[14]\ : std_logic;
SIGNAL \data~573\ : std_logic;
SIGNAL \data~574\ : std_logic;
SIGNAL \data~575\ : std_logic;
SIGNAL \data~576\ : std_logic;
SIGNAL \u1|num_a_s[6]~81\ : std_logic;
SIGNAL \u1|num_a_s[6]~81COUT1_104\ : std_logic;
SIGNAL \u1|num_a_s[7]\ : std_logic;
SIGNAL \u1|num_a[7]\ : std_logic;
SIGNAL \u2|num_a_s[6]~81\ : std_logic;
SIGNAL \u2|num_a_s[6]~81COUT1_104\ : std_logic;
SIGNAL \u2|num_a_s[7]\ : std_logic;
SIGNAL \u2|num_clk[10]\ : std_logic;
SIGNAL \u1|num_clk[15]\ : std_logic;
SIGNAL \data~577\ : std_logic;
SIGNAL \data~578\ : std_logic;
SIGNAL \data~579\ : std_logic;
SIGNAL \data~580\ : std_logic;
SIGNAL \delay[0]\ : std_logic;
SIGNAL \delay[0]~65\ : std_logic;
SIGNAL \delay[0]~65COUT1_95\ : std_logic;
SIGNAL \delay[1]\ : std_logic;
SIGNAL \delay[1]~69\ : std_logic;
SIGNAL \delay[1]~69COUT1_97\ : std_logic;
SIGNAL \delay[2]\ : std_logic;
SIGNAL \delay[2]~57\ : std_logic;
SIGNAL \delay[2]~57COUT1_99\ : std_logic;
SIGNAL \delay[3]\ : std_logic;
SIGNAL \rtl~432\ : std_logic;
SIGNAL \delay[3]~61\ : std_logic;
SIGNAL \delay[3]~61COUT1_100\ : std_logic;
SIGNAL \delay[4]\ : std_logic;
SIGNAL \delay[4]~73\ : std_logic;
SIGNAL \delay[5]\ : std_logic;
SIGNAL \delay[5]~77\ : std_logic;
SIGNAL \delay[5]~77COUT1_102\ : std_logic;
SIGNAL \delay[6]\ : std_logic;
SIGNAL \delay[6]~81\ : std_logic;
SIGNAL \delay[6]~81COUT1_104\ : std_logic;
SIGNAL \delay[7]\ : std_logic;
SIGNAL \rtl~433\ : std_logic;
SIGNAL \rtl~7\ : std_logic;
SIGNAL int2_v : std_logic;
SIGNAL int1_v : std_logic;
SIGNAL \process0~0\ : std_logic;
SIGNAL \u1|ALT_INV_p_b:lastone\ : std_logic;
SIGNAL \u2|ALT_INV_p_b:lastone\ : std_logic;

BEGIN

ww_ain <= ain;
ww_bin <= bin;
ww_clkin <= clkin;
ww_sel <= sel;
data <= ww_data;
intermit <= ww_intermit;
ww_devoe <= devoe;
ww_devclrn <= devclrn;
ww_devpor <= devpor;
\u1|ALT_INV_p_b:lastone\ <= NOT \u1|p_b:lastone\;
\u2|ALT_INV_p_b:lastone\ <= NOT \u2|p_b:lastone\;

\clkin~I\ : maxii_io
-- pragma translate_off
GENERIC MAP (
	operation_mode => "input")
-- pragma translate_on
PORT MAP (
	oe => GND,
	padio => ww_clkin,
	combout => \clkin~combout\);

\ain~I\ : maxii_io
-- pragma translate_off
GENERIC MAP (