item_new2.vhd

对硅微谐振式加速度计的数据采集电路开展研究工作

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;

ENTITY item_new2 IS
	PORT
	(
		ain,bin,clkin		: IN	STD_LOGIC;
		sel					: IN    STD_LOGIC_VECTOR(2 DOWNTO 0);
		data				: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		intermit			: OUT	STD_LOGIC
	);
END item_new2;

ARCHITECTURE a OF item_new2 IS
COMPONENT itemnew3_2
	PORT
	(
		a,clk	: IN	STD_LOGIC;
		num_a	: OUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		num_clk : OUT	STD_LOGIC_VECTOR(20 DOWNTO 0);
		int0	: OUT   STD_LOGIC
	);
END COMPONENT;
	SIGNAL aout,bout		: STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL acout,bcout		: STD_LOGIC_VECTOR(20 DOWNTO 0);
	SIGNAL int1 : STD_LOGIC;
	SIGNAL int2 : STD_LOGIC;
BEGIN
data	<=	aout(7 downto 0) WHEN sel="000" ELSE
			bout(7 downto 0) WHEN sel="001" ELSE
			acout(7 downto 0) WHEN sel="010" ELSE
			acout(15 downto 8) WHEN sel="011" ELSE
			bcout(2 downto 0) & acout(20 downto 16) WHEN sel="100" ELSE
			bcout(10 downto 3)  WHEN sel="101" ELSE
			bcout(18 downto 11) WHEN sel="110" ELSE
			"111111" & bcout(20 downto 19) WHEN sel="111" ELSE
			"111111" & bcout(20 downto 19);
			
u2:itemnew3_2 port map(a=>bin,clk=>clkin,num_a=>bout,num_clk=>bcout,int0=>int2);
u1:itemnew3_2 port map(a=>ain,clk=>clkin,num_a=>aout,num_clk=>acout,int0=>int1);

PROCESS (int1,int2,clkin)
	VARIABLE int1_v,int2_v	:	STD_LOGIC:='0';
	VARIABLE delay			:	STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN

	if(int2'event and int2='1')then int2_v:='1';end if;
	if(int1'event and int1='1')then int1_v:='1';end if;
	if(int2_v='1' and int1_v='1')then 
		intermit<='0';
		if(clkin'event and clkin='1')then delay:=delay+1;end if;
	else
		intermit<='1';delay:="00000000";
	end if;
	if(delay="11111111")then int2_v:='0';int1_v:='0';end if;
END PROCESS;

END a;