item_new2.qsf

对硅微谐振式加速度计的数据采集电路开展研究工作

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		item_new2_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY item_new2
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:00:21  AUGUST 17, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "PrimeTime (VHDL)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_timing_analysis
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_timing_analysis
set_global_assignment -name VHDL_FILE item_new2.vhd
set_location_assignment PIN_97 -to ain
set_location_assignment PIN_99 -to bin
set_location_assignment PIN_12 -to clkin
set_location_assignment PIN_75 -to data[0]
set_location_assignment PIN_74 -to data[1]
set_location_assignment PIN_73 -to data[2]
set_location_assignment PIN_72 -to data[3]
set_location_assignment PIN_71 -to data[4]
set_location_assignment PIN_70 -to data[5]
set_location_assignment PIN_69 -to data[6]
set_location_assignment PIN_68 -to data[7]
set_location_assignment PIN_50 -to intermit
set_location_assignment PIN_53 -to sel[0]
set_location_assignment PIN_52 -to sel[1]
set_location_assignment PIN_51 -to sel[2]