📄 altera_avalon_nec_tft_lcd_controller.vhd
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-- Copyright (C) 2005 altera Electronics Inc.
--
--
-- This source file may be used and distributed without restriction provided that this copyright statement is not removed from the
-- file and that any derivative work contains the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
-- ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Module: altera_avalon_nec_tft_lcd_controller
--
-- Date Created: April 16, 2005
--
-- Author: SJK
--
-- Revision History:
--
-- Date: Revision Description
--
-- 11/10/05 1.0 Initial Release
--
--
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--
-- TFT LCD Controller, Avalon Custom Peripheral
--
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY altera_avalon_nec_tft_lcd_controller IS
GENERIC
(
HORIZ_RES : INTEGER := 240;
VERT_RES : INTEGER := 320
);
PORT
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
-- Avalon Slave interface
read : in STD_LOGIC;
readdata : out STD_LOGIC_VECTOR(31 downto 0);
write : in STD_LOGIC;
writedata : in STD_LOGIC_VECTOR(31 downto 0);
address : in STD_LOGIC_VECTOR(8 downto 0);
chipselect : in STD_LOGIC;
irq : out STD_LOGIC;
-- Avalon Master interface
clk_mp : in STD_LOGIC;
read_mp : out STD_LOGIC;
waitrequest : in STD_LOGIC;
burstcount : out STD_LOGIC_VECTOR(3 downto 0);
readdatavalid : in STD_LOGIC;
readdata_mp : in STD_LOGIC_VECTOR(31 downto 0);
address_mp : out STD_LOGIC_VECTOR(31 downto 0);
-- LCD interface
tclk : in STD_LOGIC; -- sync clock for tc logic
BL_EN : out STD_LOGIC; -- enable backlight power supply
PS_EN : out STD_LOGIC; -- enable LCD power supply
HCK : out STD_LOGIC; -- horiz clock
STB : out STD_LOGIC; -- horiz. data latch pulse
HSP : out STD_LOGIC; -- horiz sync pulse
R : out STD_LOGIC_VECTOR(5 downto 0); -- red pixel data bus
G : out STD_LOGIC_VECTOR(5 downto 0); -- green pixel data bus
B : out STD_LOGIC_VECTOR(5 downto 0); -- blue pixel data bus
AP : out STD_LOGIC; -- bias circuit on/off control
POL : out STD_LOGIC; -- polarity
VCK : out STD_LOGIC; -- vert clock
VOE : out STD_LOGIC; -- vert gate drivers oe
VSP : out STD_LOGIC; -- vert sync pulse
INV : out STD_LOGIC -- data signal invert
);
END altera_avalon_nec_tft_lcd_controller;
ARCHITECTURE a OF altera_avalon_nec_tft_lcd_controller IS
-- video fifo signals
SIGNAL fifo_data_in : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL fifo_data_out : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL fifo_rdreq : STD_LOGIC;
SIGNAL fifo_wrreq : STD_LOGIC;
SIGNAL fifo_empty : STD_LOGIC;
SIGNAL fifo_usedw : STD_LOGIC_VECTOR(7 downto 0);
SIGNAL fifo_aclear : STD_LOGIC;
-- palette lut signals
SIGNAL palette_wren : STD_LOGIC;
SIGNAL palette_q : STD_LOGIC_VECTOR(17 downto 0);
-- fifo data out mux control
SIGNAL video_lane_select : STD_LOGIC_VECTOR(1 downto 0);
-- pixel video data paths
SIGNAL RGB : STD_LOGIC_VECTOR(17 downto 0);
SIGNAL bpp_16_data_out : STD_LOGIC_VECTOR(17 downto 0);
SIGNAL bpp_8_data_out : STD_LOGIC_VECTOR(17 downto 0);
SIGNAL bpp_mandel_data_out : STD_LOGIC_VECTOR(17 downto 0);
-- color lut data path
SIGNAL lut_data : STD_LOGIC_VECTOR(7 downto 0);
-- register decode signals
CONSTANT CR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := "00"; -- 0x00
CONSTANT SR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- 0x01
CONSTANT NBA_ADDR : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- 0x02
CONSTANT ISR_ADDR : STD_LOGIC_VECTOR(1 downto 0) := "11"; -- 0x03
-- control & status registers
SIGNAL cr : STD_LOGIC_VECTOR(6 downto 0);
SIGNAL read_isr : STD_LOGIC;
-- cr control functions
SIGNAL enable_dma : STD_LOGIC;
SIGNAL palette_mode : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL vert_scan_dir : STD_LOGIC;
SIGNAL interrupt_enable : STD_LOGIC;
-- signals that cannot update until eof has occurred. sw can update these assynchronously and whack the display. we prevent this.
SIGNAL updated_palette_mode : STD_LOGIC_VECTOR(1 downto 0);
SIGNAL updated_enable_dma : STD_LOGIC;
-- palette modes are defined by video data bits allocated per LCD pixel
CONSTANT BPP_18 : STD_LOGIC_VECTOR(1 downto 0) := "00"; -- 64 x 64 x 64 = 262,144 colors
CONSTANT BPP_16 : STD_LOGIC_VECTOR(1 downto 0) := "01"; -- 32 x 64 x 32 = 32,768 colors
CONSTANT BPP_8 : STD_LOGIC_VECTOR(1 downto 0) := "10"; -- 256 colors
CONSTANT BPP_MANDEL : STD_LOGIC_VECTOR(1 downto 0) := "11"; -- custom mandelbrot palette
SIGNAL fifo_ready_for_data : STD_LOGIC;
SIGNAL sr_dataout : STD_LOGIC;
-- dma address registers
SIGNAL nba : STD_LOGIC_VECTOR(31 downto 0);
-- dma functions
-- SIGNAL dma_count : INTEGER RANGE 0 TO (HORIZ_RES * VERT_RES) - 1; -- max of 76800 transfer in BPP_18 palette_mode sjk
SIGNAL dma_count : INTEGER RANGE 0 TO (HORIZ_RES * VERT_RES) ; -- max of 76800 transfer in BPP_18 palette_mode
CONSTANT MAX_COUNT_BPP_18 : INTEGER := HORIZ_RES * VERT_RES;
CONSTANT MAX_COUNT_BPP_16 : INTEGER := HORIZ_RES * VERT_RES/2;
CONSTANT MAX_COUNT_BPP_8 : INTEGER := HORIZ_RES * VERT_RES/4;
SIGNAL dma_current_address : STD_LOGIC_VECTOR(31 downto 0);
TYPE dma_state_type is (idle, address_phase, data_phase);
SIGNAL dma_next_state : dma_state_type;
CONSTANT MAX_BURST_COUNT : INTEGER := 8;
SIGNAL current_burst_count : INTEGER RANGE 0 TO MAX_BURST_COUNT;
-- internal version of irq signal, satisfies modelsim synth. requirements
SIGNAL irq_int : STD_LOGIC;
-- last line indicator from the timing control module
SIGNAL end_of_frame : STD_LOGIC;
-- clk signals sync'ed to tclk domain
SIGNAL palette_mode_tclk : STD_LOGIC_VECTOR(1 downto 0);
-- signals from the timing control unit
SIGNAL fifo_data_available : STD_LOGIC;
SIGNAL palette_mode_lock : STD_LOGIC_VECTOR(1 downto 0);
-- declare the video fifo
COMPONENT fifo_256x32 IS
PORT
(
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
rdclk : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
aclr : IN STD_LOGIC := '0';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
-- declare the 256 color palette table
COMPONENT palette_memory IS
PORT
(
data : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (17 DOWNTO 0)
);
END COMPONENT;
COMPONENT timing_control IS
GENERIC
(
HORIZ_RES : INTEGER := 240;
VERT_RES : INTEGER := 320
);
PORT
(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
palette_mode : in STD_LOGIC_VECTOR(1 downto 0);
vert_scan_dir : in STD_LOGIC;
video_lane_select_ext : out STD_LOGIC_VECTOR(1 downto 0);
fifo_rdreq_ext : out STD_LOGIC;
fifo_empty : in STD_LOGIC;
fifo_data_available_ext : out STD_LOGIC;
palette_mode_lock_ext : out STD_LOGIC_VECTOR(1 downto 0);
HCK : out STD_LOGIC; -- horiz clock
STB : out STD_LOGIC; -- horiz. data latch pulse
HSP : out STD_LOGIC; -- horiz sync pulse
AP : out STD_LOGIC; -- bias circuit on/off control
POL : out STD_LOGIC; -- polarity
VCK : out STD_LOGIC; -- vert clock
VOE : out STD_LOGIC; -- vert gate drivers oe
VSP : out STD_LOGIC; -- vert sync pulse
INV : out STD_LOGIC -- data signal invert
);
END COMPONENT;
begin
------------------------------------------------------------------------------------------------------------------------------------------------
--
-- Control/Status Registers
--
------------------------------------------------------------------------------------------------------------------------------------------------
-- create control & status registers
register_access: process (clk, reset, chipselect, cr, nba)
begin
cr <= cr;
nba <= nba;
if reset = '1' then
cr <= (others => '0');
nba <= (others => '0');
elsif (clk'EVENT AND clk = '1') then
if (chipselect = '1') and (address(8) = '0') then
case address(1 downto 0) is
when CR_ADDR =>
if (write = '1') then
cr(6 downto 0) <= writedata(6 downto 0);
elsif (read = '1') then
readdata <= "0000000000000000000000000" & cr;
end if;
when SR_ADDR =>
if (read = '1') then
readdata <= "0000000000000000000000000000000" & sr_dataout;
end if;
when NBA_ADDR =>
if (write = '1') then
nba(31 downto 0) <= writedata(31 downto 0);
elsif (read = '1') then
readdata <= nba;
end if;
when others =>
cr <= cr;
nba <= nba;
readdata <= "00000000000000000000000000000000";
end case;
else
cr <= cr;
nba <= nba;
end if;
else
cr <= cr;
nba <= nba;
end if;
end process;
-- status register bit functions
sr_dataout <= irq_int;
enable_dma <= cr(0);
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