timing_control.vhd

quartus II-sopc builder avalon总线LCD控制IPCORE

		
			AP_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
		
			if display_data_valid = '1' then
			
				if (four_count = 3) and (HCK_int = '1') then
			
					if horiz_count > Tvck_stb + Tstb_ap and horiz_count < Tvck_stb + Tstb_ap + PWap then
						AP_int <= '1';
					else
						AP_int <= '0';
					end if;
				else
					AP_int <= AP_int;
				end if;
			end if;
		else
			AP_int <= AP_int;
		end if;
	end process;
	
	

-- create frame rate timing

gen_vert_count : process (clk, reset, HCK_int, four_count, horiz_count, vert_count, pol_init)				

	begin
	
		if reset = '1' then
		
			vert_count <= 0;
			pol_init <= '0';
			
		elsif (clk'EVENT and clk = '1') then
		
			if (HCK_int = '1') and (four_count = 3) and (horiz_count = MAX_HCOUNT) then
				
				if vert_count < MAX_VCOUNT then
					vert_count <= vert_count + 1;
					pol_init <= pol_init;
				else
					vert_count <= 0;
					pol_init <= not pol_init;
				end if;
			else
				vert_count <= vert_count;
				pol_init <= pol_init;
			end if;
				
		end if;
	end process;
	
-- create frame sync signals
	
gen_VCK_VOE : process (clk, reset, vert_count, VCK_int, VOE_int)

	begin
		if reset = '1' then
			VCK_int <= '0';
			VOE_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
			if (four_count = 3) and (HCK_int = '1') then
				if horiz_count >= 0 and horiz_count < Tvck_stb + PWstb then
					VCK_int <= '1';
					VOE_int <= '1';
				else
					VCK_int <= '0';
					VOE_int <= '0';
				end if;
			else
				VCK_int <= VCK_int;
				VOE_int <= VOE_int;
			end if;
		else
			VCK_int <= VCK_int;
			VOE_int <= VOE_int;
		end if;
	end process;
	
-- create reverse polarisation signal

gen_POL : process (clk, reset, four_count, HCK_int, horiz_count, vert_count, POL_int, pol_init)

	begin
		if reset = '1' then
			POL_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
			if (four_count = 3) and (HCK_int = '1') and horiz_count = 2 and vert_count = 0 then 
				POL_int <= pol_init;
			elsif (four_count = 3) and (HCK_int = '1') and horiz_count = 2 then 
				POL_int <= not POL_int;
			else
				POL_int <= POL_int;
			end if;
		else
			POL_int <= POL_int;
		end if;
	end process;
	
-- create vertical sync pulse

gen_VSP : process (clk, reset, four_count, HCK_int, horiz_count, vert_count, VSP_int)

	begin
		if reset = '1' then
			VSP_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
			if vert_count = VERT_BP then
				if (four_count = 3) and (HCK_int = '1') and horiz_count >= HORIZ_BP - 1 then 
					VSP_int <= '1';
				elsif (four_count = 3) and (HCK_int = '1') and horiz_count < HORIZ_BP - 1 then 
					VSP_int <= '0';
				else 
					VSP_int <= VSP_int;
				end if;
			elsif vert_count = VERT_BP + 1 then
				if (four_count = 3) and (HCK_int = '1') and horiz_count <= HORIZ_BP - 1 then 
					VSP_int <= '1';
				elsif (four_count = 3) and (HCK_int = '1') and horiz_count > HORIZ_BP - 1 then 
					VSP_int <= '0';
				else 
					VSP_int <= VSP_int;
				end if;
			else
				VSP_int <= VSP_int;
			end if;
		else
			VSP_int <= VSP_int;
		end if;
	end process;
	
	
-- create tc start of frame synch signal. will only assert if there is data available in the fifo

gen_fifo_data_available : process (clk, reset, four_count, horiz_count, vert_count, fifo_empty, fifo_data_available)				

	begin
	
		if reset = '1' then
		
			fifo_data_available <= '0';
			
		elsif (clk'EVENT and clk = '0') then
		
			if (vert_count = VERT_BP) and  (horiz_count = HORIZ_BP-8) and (fifo_empty = '0') then
				fifo_data_available <= '1';
			elsif (vert_count = VERT_BP) and  (horiz_count = HORIZ_BP-8) and (fifo_empty = '1') then
				fifo_data_available <= '0';			
			else
				fifo_data_available <= fifo_data_available;
			end if;
		else
			fifo_data_available <= fifo_data_available;
		end if;
			
	end process;
	
fifo_data_available_ext	<= fifo_data_available;
	
	
-- create locked version of palette mode signal. only allow it to be updated when current frame is complete

gen_palette_mode_lock : process (clk, reset, four_count, horiz_count, vert_count, palette_mode, palette_mode_lock )				

	begin
	
		if reset = '1' then
		
			palette_mode_lock <= "00";
			
		elsif (clk'EVENT and clk = '0') then
		
			if (vert_count = VERT_BP) and  (horiz_count = HORIZ_BP-8) and (fifo_empty = '0') then			-- only allow it to be updated
				palette_mode_lock <= palette_mode;															-- before the visible frame begins
			else
				palette_mode_lock <= palette_mode_lock;
			end if;
		else
			palette_mode_lock <= palette_mode_lock;
		end if;
			
	end process;
	
palette_mode_lock_ext <= palette_mode_lock;
	
	
-- create fifo dataout mux selector signal

gen_video_lane_sel : process (clk, reset, four_count, HCK_int, horiz_count, fifo_data_available, palette_mode_lock, video_lane_select)				

	begin
	
		if reset = '1' then
		
			video_lane_select <= "00";
			
		elsif (clk'EVENT and clk = '0') then
		
			if fifo_data_available = '1' and (vert_count = VERT_BP) and  (horiz_count = HORIZ_BP-4) then
				video_lane_select <= "00";
			else
--				if (four_count) = 3 and (HCK_int = '1') and (horiz_count > HORIZ_BP-1) and (horiz_count < (HORIZ_RES + HORIZ_BP )) then    -- uncomment when not building ref design. comment line below
				if (four_count) = 3 and (HCK_int = '1') and (horiz_count > HORIZ_BP-2) and (horiz_count < (HORIZ_RES + HORIZ_BP -1 )) then
				
					if palette_mode_lock = BPP_18 then
						video_lane_select <= "11";
					elsif palette_mode_lock = BPP_16 then
						video_lane_select <= video_lane_select + "10";
					elsif palette_mode_lock = BPP_8 then
						video_lane_select <= video_lane_select + "01";
					elsif palette_mode_lock = BPP_MANDEL then
						video_lane_select <= video_lane_select + "01";
					else
						video_lane_select <= video_lane_select;
					end if;
				else
					video_lane_select <= video_lane_select;
				end if;
			end if;
		else
			video_lane_select <= video_lane_select;
		end if;
			
	end process;
	
			
-- create fifo_rdreq		

gen_rdreq : process (clk, reset, four_count, HCK_int, horiz_count, vert_count, fifo_data_available, fifo_rdreq, palette_mode_lock, video_lane_select)				

	begin
	
		if reset = '1' then
		
			fifo_rdreq <= '0';
			
		elsif (clk'EVENT and clk = '0') then
		
			if fifo_data_available = '1' and (vert_count >= VERT_BP) and (vert_count <= MAX_VCOUNT) and (fifo_empty = '0') then

--				if (four_count) = 3 and (HCK_int = '1') and (horiz_count > HORIZ_BP-1) and (horiz_count < (HORIZ_RES + HORIZ_BP ) )then     -- uncomment when not building ref design. comment line below
				if (four_count) = 3 and (HCK_int = '1') and (horiz_count > HORIZ_BP-2) and (horiz_count < (HORIZ_RES + HORIZ_BP -1 ) )then     

					if (palette_mode_lock = BPP_18) and (video_lane_select = "11") then
						fifo_rdreq <= '1';
					elsif (palette_mode_lock = BPP_16) and (video_lane_select = "10") then
						fifo_rdreq <= '1';
					elsif (palette_mode_lock = BPP_8) and (video_lane_select = "11") then
						fifo_rdreq <= '1';
					elsif (palette_mode_lock = BPP_MANDEL) and (video_lane_select = "11") then
						fifo_rdreq <= '1';
					else
						fifo_rdreq <= '0';
					end if;
				else
					fifo_rdreq <= '0';
				end if;
			else
				fifo_rdreq <= '0';
			end if;
		else
			fifo_rdreq <= fifo_rdreq;
		end if;
			
	end process;
	
	
-- drive external lcd control signals, satisfy crazy vhdl/modelsim syntax requirements

INV_int <= '0';

HCK <= HCK_int;
STB <= STB_int;
HSP <= HSP_int;
AP <= AP_int;
POL <= POL_int;
VCK <= VCK_int;
VOE <= VOE_int;
VSP <= VSP_int;
INV <= INV_int;

fifo_rdreq_ext <= fifo_rdreq;
video_lane_select_ext <= video_lane_select;
	
	
end;