timing_control.vhd

quartus II-sopc builder avalon总线LCD控制IPCORE

-- 			Copyright (C) 2005 altera Electronics Inc.                         
--                    		                               
--                                                             
-- 			This source file may be used and distributed without restriction provided that this copyright statement is not removed from the 
--			file and that any derivative work contains the original copyright notice and the associated disclaimer.
--                                                             
--			THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 
--			WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 
--			ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
--			SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  
-- 			LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  
-- 			OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         
-- 			POSSIBILITY OF SUCH DAMAGE.
--
--
-------------------------------------------------------------------------------------------------------------------------------------------------
--
--	Module: timing_control
--
--	Date Created: April 16, 2005
--
--	Author: SJK
--
--	Revision History:
--
--	Date:			Revision	Description
--	
--	11/10/05		1.0		Initial Release
--
--	Notes:
--
--	1.			gen_video_lane_sel and gen_rdreq commented line due to rgb_demux in ref design
--
--
------------------------------------------------------------------------------------------------------------------------------------------------			


  LIBRARY ieee;


USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

ENTITY timing_control IS

	GENERIC
	(
		HORIZ_RES			: INTEGER := 240;
		VERT_RES			: INTEGER := 320
	);
	PORT
	(

		clk						: in		STD_LOGIC;
		reset					: in		STD_LOGIC;
		
	--	Control Register signals
		
		palette_mode			: in		STD_LOGIC_VECTOR(1 downto 0);
		vert_scan_dir			: in		STD_LOGIC;
		
	-- RGB fifo control

		video_lane_select_ext	: out		STD_LOGIC_VECTOR(1 downto 0);
		fifo_rdreq_ext			: out		STD_LOGIC;
		fifo_empty				: in		STD_LOGIC;
		
		fifo_data_available_ext	: out		STD_LOGIC;
		palette_mode_lock_ext	: out		STD_LOGIC_VECTOR(1 downto 0);
		
	-- LCD interface
	
		HCK						: out		STD_LOGIC;							--	horiz clock
		STB						: out		STD_LOGIC;							--	horiz. data latch pulse
		HSP						: out		STD_LOGIC;							--	horiz sync pulse
		AP						: out		STD_LOGIC;							--	bias circuit on/off control
		POL						: out		STD_LOGIC;							--	polarity
		VCK						: out		STD_LOGIC;							--	vert clock
		VOE						: out		STD_LOGIC;							--	vert gate drivers oe
		VSP						: out		STD_LOGIC;							--	vert sync pulse
		INV						: out		STD_LOGIC							--	data signal invert 
	);
	
END timing_control;

ARCHITECTURE a OF timing_control IS



-- lcd controller row & column timing


-- horiz_count = HCK / PPvck = 6.25 MHz / 19.841 KHz = 315 

CONSTANT	PWstb						: INTEGER := 4;	
CONSTANT	Tstb_hsp					: INTEGER := 4;	
CONSTANT	Tstb_ap						: INTEGER := 18;						-- Tstb-ap = 6uS typ	
CONSTANT	PWap						: INTEGER := 90;						-- PWap = 30uS typ	
CONSTANT	PWhsp						: INTEGER := 1;	
CONSTANT	Tvck_stb					: INTEGER := 19;						-- Tvck-stb = 3uS typ
CONSTANT	PWvoe						: INTEGER := Tvck_stb + PWstb;	

CONSTANT	HORIZ_BP					: INTEGER := Tvck_stb + Tstb_hsp + PWhsp + 1;	
CONSTANT	HORIZ_FP					: INTEGER := 50;						-- PPvck = 19.841 KHz

-- vert_count = 19.841 KHz / 60 Hz = 330

CONSTANT	VERT_BP						: INTEGER := 10;
CONSTANT	VERT_FP						: INTEGER := 0;							-- 1/PPvsp = 60 Hz

CONSTANT	MAX_HCOUNT					: INTEGER := HORIZ_RES + HORIZ_BP + HORIZ_FP - 1;
CONSTANT	MAX_VCOUNT					: INTEGER := VERT_RES + VERT_BP + VERT_FP - 1;

SIGNAL		four_count					: INTEGER RANGE 0 TO 3;
SIGNAL		horiz_count					: INTEGER RANGE 0 TO (MAX_HCOUNT);
SIGNAL		vert_count					: INTEGER RANGE 0 TO (MAX_VCOUNT);
SIGNAL		frame_count					: INTEGER RANGE 0 TO 2;

-- internal version of external lcd control signals, satisfies modelsim synth. requirements

SIGNAL		HCK_int						: STD_LOGIC;							--	pixel clock (6.25MHz or 160nS per cycle)
SIGNAL		STB_int						: STD_LOGIC;							--	horiz. data latch pulse
SIGNAL		HSP_int						: STD_LOGIC;							--	horiz sync pulse
SIGNAL		AP_int						: STD_LOGIC;							--	bias circuit on/off control
SIGNAL		POL_int						: STD_LOGIC;							--	polarity
SIGNAL		VCK_int						: STD_LOGIC;							--	vert clock
SIGNAL		VOE_int						: STD_LOGIC;							--	vert gate drivers oe
SIGNAL		VSP_int						: STD_LOGIC;							--	vert sync pulse
SIGNAL		INV_int						: STD_LOGIC;							--	data signal invert

SIGNAL		pol_init					: STD_LOGIC;							--	polarity initialisation

-- internal version of RGB FIFO control signals, satisfies modelsim synth. requirements

SIGNAL		fifo_data_available			: STD_LOGIC;

SIGNAL		video_lane_select			: STD_LOGIC_VECTOR(1 downto 0);
SIGNAL		fifo_rdreq					: STD_LOGIC;

-- do not allow palette mode input to processes change during active frame

SIGNAL		palette_mode_lock			: STD_LOGIC_VECTOR(1 downto 0);

-- palette modes are defined by video data bits allocated per LCD pixel

CONSTANT	BPP_18						: STD_LOGIC_VECTOR(1 downto 0) := "00";			--	64 x 64 x 64 = 262,144 colors
CONSTANT	BPP_16						: STD_LOGIC_VECTOR(1 downto 0) := "01";			--	32 x 64 x 32 = 32,768 colors
CONSTANT	BPP_8						: STD_LOGIC_VECTOR(1 downto 0) := "10";			--	256 colors
CONSTANT	BPP_MANDEL					: STD_LOGIC_VECTOR(1 downto 0) := "11";			--	custom mandelbrot palette

SIGNAL		display_data_valid			: STD_LOGIC;									

begin

display_data_valid <= '1' when (vert_count > (VERT_BP - 1)) else
					  '0';

-- create 5MHz pixel clock
	
fifty_MHz_div_by_4 : process (clk, reset, four_count)				

	begin
	
		if reset = '1' then
		
			four_count <= 0;
			
		elsif (clk'EVENT and clk = '1') then
			
			if four_count = 3 then
				four_count <= 0;
			else
				four_count <= four_count + 1;
			end if;
		else
			four_count <= four_count;
		end if;
			
	end process;
	
-- create symetrical HCK by dividing by 2
	
gen_pixel_clock : process (clk, reset, four_count, HCK_int)					

	begin
	
		if reset = '1' then
		
			HCK_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
		
			if 	four_count = 3 then
				HCK_int <= not HCK_int;
			else
				HCK_int <= HCK_int;
			end if;

		end if;
			
	end process;
	
-- create line rate timing for CLS
	
gen_horiz_count : process (clk, reset, HCK_int, four_count, horiz_count)		

	begin
	
		if reset = '1' then
		
			horiz_count <= 0;
			
		elsif (clk'EVENT and clk = '1') then
		
			if (four_count = 3) and (HCK_int = '1') then
			
				if horiz_count < MAX_HCOUNT then
					horiz_count <= horiz_count + 1;
				else
					horiz_count <= 0;
				end if;
			else
				horiz_count <= horiz_count;
			end if;
				
		end if;
			
	end process;
	
-- create line sync signals	
	
gen_STB: process (clk, reset, four_count, HCK_int, STB_int, horiz_count, vert_count)		

	begin
	
		if reset = '1' then
		
			STB_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
		
			if display_data_valid = '1' then
			
				if (four_count = 3) and (HCK_int = '1') then
			
					if horiz_count >= Tvck_stb and horiz_count < Tvck_stb + PWstb then
						STB_int <= '1';
					else
						STB_int <= '0';
					end if;
				else
					STB_int <= STB_int;
				end if;
			else
				STB_int <= '0';
			end if;
		end if;
	end process;
	
gen_HSP: process (clk, reset, four_count, HCK_int, HSP_int, horiz_count, vert_count)		

	begin
	
		if reset = '1' then
		
			HSP_int <= '0';
			
		elsif (clk'EVENT and clk = '1') then
		
			if display_data_valid = '1' then
			
				if (four_count = 3) and (HCK_int = '1') then
			
					if horiz_count = Tvck_stb + PWstb then
						HSP_int <= '1';
					else
						HSP_int <= '0';
					end if;
				else
					HSP_int <= HSP_int;
				end if;
			end if;
		else
			HSP_int <= HSP_int;
		end if;
	end process;
	
	
gen_AP: process (clk, reset, four_count, HCK_int, AP_int, horiz_count, vert_count)		

	begin
	
		if reset = '1' then