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}
PORT readdatavalid
{
width = "1";
width_expression = "";
direction = "input";
type = "readdatavalid";
is_shared = "0";
}
PORT readdata_mp
{
width = "32";
width_expression = "";
direction = "input";
type = "readdata";
is_shared = "0";
}
PORT address_mp
{
width = "32";
width_expression = "";
direction = "output";
type = "address";
is_shared = "0";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "NEC LCD Controller";
technology = "altera";
}
WIZARD_UI the_wizard_ui
{
title = "NEC LCD Controller - {{ $MOD }}";
GROUP overview
{
title = "Overview";
font = "bold";
align="left";
layout="horizontal";
TEXT {title = "Core name: altera LCD IP Core\n
Core version: 11/10/2005\n
Core source: www.niosforum.org";}
IMAGE {file = "alteralogobluesmall.gif";}
TEXT {title = " ";}
}
CONTEXT
{
H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
M = "";
SBI_ = "SYSTEM_BUILDER_INFO";
SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
SBI_avalon_master_0 = "MASTER avalon_master_0/SYSTEM_BUILDER_INFO";
}
PAGES main
{
PAGE 1
{
align = "left";
title = "<b>NEC LCD Controller 1.0</b> Settings";
layout = "vertical";
TEXT
{
title = "Built on: 2005.08.21.18:59:58";
}
TEXT
{
title = "Class name: nec_lcd_controller";
}
TEXT
{
title = "Class version: 1.0";
}
TEXT
{
title = "Component name: NEC LCD Controller";
}
TEXT
{
title = "Component Group: altera";
}
GROUP parameters
{
title = "Parameters";
layout = "form";
align = "left";
EDIT e1
{
editable = "1";
title = "HORIZ_RES:";
columns = "40";
tooltip = "default value: 240";
DATA
{
$H/horiz_res = "$";
}
q = "'";
warning = "{{ if(!(regexp('ugly_'+$H/horiz_res,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/horiz_res,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/horiz_res,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/horiz_res,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/horiz_res,'ugly_-?[0-9]+')))'HORIZ_RES must be numeric constant, not '+$H/horiz_res; }}";
}
EDIT e2
{
editable = "1";
title = "VERT_RES:";
columns = "40";
tooltip = "default value: 320";
DATA
{
$H/vert_res = "$";
}
q = "'";
warning = "{{ if(!(regexp('ugly_'+$H/vert_res,'ugly_[0-9]*'+$q+'[bB][01][_01]*')||regexp('ugly_'+$H/vert_res,'ugly_[0-9]*'+$q+'[hH][0-9a-fA-F][_0-9a-fA-F]*')||regexp('ugly_'+$H/vert_res,'ugly_[0-9]*'+$q+'[oO][0-7][_0-7]*')||regexp('ugly_'+$H/vert_res,'ugly_0x[0-9a-fA-F]+')||regexp('ugly_'+$H/vert_res,'ugly_-?[0-9]+')))'VERT_RES must be numeric constant, not '+$H/vert_res; }}";
}
}
}
}
}
}
CB_GENERATOR
{
top_module_name = "altera_avalon_nec_tft_lcd_controller.vhd:altera_avalon_nec_tft_lcd_controller";
emit_system_h = "1";
HDL_FILES
{
FILE
{
filepath = "hdl/altera_avalon_nec_tft_lcd_controller.vhd";
use_in_simulation = "1";
use_in_synthesis = "1";
}
FILE
{
filepath = "hdl/fifo_256x32.vhd";
use_in_simulation = "1";
use_in_synthesis = "1";
}
FILE
{
filepath = "hdl/palette_memory.vhd";
use_in_simulation = "1";
use_in_synthesis = "1";
}
FILE
{
filepath = "hdl/timing_control.vhd";
use_in_simulation = "1";
use_in_synthesis = "1";
}
}
}
COMPONENT_BUILDER
{
CACHED_HDL_INFO
{
# cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:130
# used only by Component Builder
FILE palette_memory.vhd
{
file_mod = "Sat Apr 16 10:35:32 EDT 2005";
quartus_map_start = "Mon Apr 18 23:08:08 EDT 2005";
quartus_map_finished = "Mon Apr 18 23:08:10 EDT 2005";
#found 1 valid modules
WRAPPER palette_memory
{
CLASS palette_memory
{
MODULE_DEFAULTS
{
class = "palette_memory";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Address_Width = "0";
Address_Alignment = "dynamic";
Data_Width = "8";
Has_Base_Address = "0";
Has_IRQ = "0";
}
PORT_WIRING
{
PORT data
{
width = "18";
width_expression = "";
direction = "input";
type = "export";
}
PORT wren
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT wraddress
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT rdaddress
{
width = "8";
width_expression = "";
direction = "input";
type = "export";
}
PORT clock
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
}
PORT q
{
width = "18";
width_expression = "";
direction = "output";
type = "export";
}
}
}
}
USER_INTERFACE
{
USER_LABELS
{
name = "palette_memory";
technology = "imported components";
}
}
CB_GENERATOR
{
top_module_name = "palette_memory";
emit_system_h = "0";
HDL_FILES
{
FILE
{
filepath = "C:/max2work/avalon_peripherals/altera_avalon_nec_tft_lcd_controller/standard/palette_memory.vhd";
use_in_simulation = "1";
use_in_synthesis = "1";
}
}
}
}
}
}
FILE altera_avalon_nec_tft_lcd_controller.vhd
{
file_mod = "Sun Aug 21 18:57:24 EDT 2005";
quartus_map_start = "Sun Aug 21 18:57:38 EDT 2005";
quartus_map_finished = "Sun Aug 21 18:57:40 EDT 2005";
#found 1 valid modules
WRAPPER altera_avalon_nec_tft_lcd_controller
{
CLASS altera_avalon_nec_tft_lcd_controller
{
MODULE_DEFAULTS
{
class = "altera_avalon_nec_tft_lcd_controller";
class_version = "1.0";
SYSTEM_BUILDER_INFO
{
Instantiate_In_System_Module = "1";
}
SLAVE avalon_slave_0
{
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
}
PORT_WIRING
{
PORT clk
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
}
PORT reset
{
width = "1";
width_expression = "";
direction = "input";
type = "reset";
is_shared = "0";
}
PORT read
{
width = "1";
width_expression = "";
direction = "input";
type = "read";
is_shared = "0";
}
PORT readdata
{
width = "32";
width_expression = "";
direction = "output";
type = "readdata";
is_shared = "0";
}
PORT write
{
width = "1";
width_expression = "";
direction = "input";
type = "write";
is_shared = "0";
}
PORT writedata
{
width = "32";
width_expression = "";
direction = "input";
type = "writedata";
is_shared = "0";
}
PORT address
{
width = "9";
width_expression = "";
direction = "input";
type = "address";
is_shared = "0";
}
PORT chipselect
{
width = "1";
width_expression = "";
direction = "input";
type = "chipselect";
is_shared = "0";
}
PORT irq
{
width = "1";
width_expression = "";
direction = "output";
type = "irq";
is_shared = "0";
}
PORT clk_mp
{
width = "1";
width_expression = "";
direction = "input";
type = "clk";
is_shared = "0";
}
PORT read_mp
{
width = "1";
width_expression = "";
direction = "output";
type = "read";
is_shared = "0";
}
PORT waitrequest
{
width = "1";
width_expression = "";
direction = "input";
type = "waitrequest";
is_shared = "0";
}
PORT burstcount
{
width = "4";
width_expression = "";
direction = "output";
type = "burstcount";
is_shared = "0";
}
PORT readdatavalid
{
width = "1";
width_expression = "";
direction = "input";
type = "readdatavalid";
is_shared = "0";
}
PORT readdata_mp
{
width = "32";
width_expression = "";
direction = "input";
type = "readdatat";
is_shared = "0";
}
PORT address_mp
{
width = "32";
width_expression = "";
direction = "output";
type = "address";
is_shared = "0";
}
PORT tclk
{
width = "1";
width_expression = "";
direction = "input";
type = "export";
is_shared = "0";
}
PORT BL_EN
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT PS_EN
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT HCK
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT STB
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT HSP
{
width = "1";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT R
{
width = "6";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT G
{
width = "6";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT B
{
width = "6";
width_expression = "";
direction = "output";
type = "export";
is_shared = "0";
}
PORT AP
{
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