coregen.log

vhdl语言写的基数分频器

# Xilinx CORE Generator 6.3i
# User = xiaoshichang
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in H:\金美通信1\vhdl程序\clk_div3\coregen.log
NEWPROJECT .
SETPROJECT .
# busformat=BusFormatAngleBracketNotRipped
# designflow=VHDL
# expandedprojectpath=H:\金美通信1\vhdl程序\clk_div3
# flowvendor=Foundation_iSE
# formalverification=None
# simulationoutputproducts=VHDL
# xilinxfamily=Virtex2
# outputoption=DesignFlow
# overwritefiles=Default
# simvendor=ModelSim
# expandedprojectpath=H:\金美通信1\vhdl程序\clk_div3
Set current Project to H:\金美通信1\vhdl程序\clk_div3
SET BusFormat = BusFormatAngleBracketNotRipped
SETXIPCPORTHOST 1041
XIPCPJSENDCORES spartan2