📄 __projnav.log
字号:
Project Navigator Auto-Make Log File-------------------------------------
deleting __projnav/clk_div3.gflFinished cleaning up project
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file F:\clk_div3/clk_div3.vhd, automatic determination of correct order of compilation of files in project file clk_div3_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.Compiling vhdl file F:\clk_div3/clk_div3.vhd in Library work.ERROR:HDLParsers:164 - F:\clk_div3/clk_div3.vhd Line 21. parse error, unexpected IDENTIFIER, expecting COMMA or COLONERROR:HDLParsers:808 - F:\clk_div3/clk_div3.vhd Line 24. = can not have such operands in this context.ERROR:HDLParsers:3312 - F:\clk_div3/clk_div3.vhd Line 26. Undefined symbol 'counter1'.ERROR:HDLParsers:808 - F:\clk_div3/clk_div3.vhd Line 27. = can not have such operands in this context.ERROR:HDLParsers:1209 - F:\clk_div3/clk_div3.vhd Line 29. counter1: Undefined symbol (last report in this block)ERROR:HDLParsers:164 - F:\clk_div3/clk_div3.vhd Line 37. parse error, unexpected IDENTIFIER, expecting COMMA or COLONERROR:HDLParsers:808 - F:\clk_div3/clk_div3.vhd Line 40. = can not have such operands in this context.ERROR:HDLParsers:3312 - F:\clk_div3/clk_div3.vhd Line 42. Undefined symbol 'counter2'.ERROR:HDLParsers:808 - F:\clk_div3/clk_div3.vhd Line 43. = can not have such operands in this context.ERROR:HDLParsers:1209 - F:\clk_div3/clk_div3.vhd Line 45. counter2: Undefined symbol (last report in this block)ERROR:HDLParsers:164 - F:\clk_div3/clk_div3.vhd Line 52. parse error, unexpected LE, expecting SEMICOLONERROR:HDLParsers:3312 - F:\clk_div3/clk_div3.vhd Line 53. Undefined symbol 'ou2_temp'.ERROR:HDLParsers:1209 - F:\clk_div3/clk_div3.vhd Line 53. ou2_temp: Undefined symbol (last report in this block)ERROR:HDLParsers:808 - F:\clk_div3/clk_div3.vhd Line 54. + can not have such operands in this context.ERROR:HDLParsers:164 - F:\clk_div3/clk_div3.vhd Line 55. parse error, unexpected IDENTIFIER, expecting PROCESS--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file F:\clk_div3/clk_div3.vhd, automatic determination of correct order of compilation of files in project file clk_div3_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file.Compiling vhdl file F:\clk_div3/clk_div3.vhd in Library work.ERROR:HDLParsers:164 - F:\clk_div3/clk_div3.vhd Line 52. parse error, unexpected LE, expecting SEMICOLONERROR:HDLParsers:3312 - F:\clk_div3/clk_div3.vhd Line 53. Undefined symbol 'ou2_temp'.ERROR:HDLParsers:1209 - F:\clk_div3/clk_div3.vhd Line 53. ou2_temp: Undefined symbol (last report in this block)ERROR:HDLParsers:808 - F:\clk_div3/clk_div3.vhd Line 54. + can not have such operands in this context.ERROR:HDLParsers:164 - F:\clk_div3/clk_div3.vhd Line 55. parse error, unexpected IDENTIFIER, expecting PROCESS--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/clk_div3/clk_div3.vhd in Library work.ERROR:HDLParsers:3312 - F:/clk_div3/clk_div3.vhd Line 52. Undefined symbol 'ou1_temp'.ERROR:HDLParsers:1209 - F:/clk_div3/clk_div3.vhd Line 52. ou1_temp: Undefined symbol (last report in this block)ERROR:HDLParsers:3312 - F:/clk_div3/clk_div3.vhd Line 53. Undefined symbol 'ou2_temp'.ERROR:HDLParsers:1209 - F:/clk_div3/clk_div3.vhd Line 53. ou2_temp: Undefined symbol (last report in this block)ERROR:HDLParsers:808 - F:/clk_div3/clk_div3.vhd Line 54. + can not have such operands in this context.--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/clk_div3/clk_div3.vhd in Library work.ERROR:HDLParsers:808 - F:/clk_div3/clk_div3.vhd Line 54. + can not have such operands in this context.--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/clk_div3/clk_div3.vhd in Library work.ERROR:HDLParsers:1411 - F:/clk_div3/clk_div3.vhd Line 54. Parameter out1 of mode out can not be associated with a formal parameter of mode in.ERROR:HDLParsers:1411 - F:/clk_div3/clk_div3.vhd Line 54. Parameter out2 of mode out can not be associated with a formal parameter of mode in.--> Total memory usage is 48404 kilobytesERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/clk_div3/clk_div3.vhd in Library work.Entity <clk_div3> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <clk_div3> (Architecture <Behavioral>).Entity <clk_div3> analyzed. Unit <clk_div3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clk_div3>. Related source file is F:/clk_div3/clk_div3.vhd. Found 2-bit down counter for signal <counter1>. Found 2-bit down counter for signal <counter2>. Found 1-bit register for signal <out1_temp>. Found 1-bit register for signal <out2_temp>. Found 2 1-bit 2-to-1 multiplexers. Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Multiplexer(s).Unit <clk_div3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 2 2-bit down counter : 2# Registers : 2 1-bit register : 2# Multiplexers : 2 1-bit 2-to-1 multiplexer : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clk_div3> ...Loading device for application Xst from file 'v150.nph' in environment C:/Program Files/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clk_div3, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s150fg456-6 Number of Slices: 5 out of 1728 0% Number of Slice Flip Flops: 6 out of 3456 0% Number of 4 input LUTs: 9 out of 3456 0% Number of bonded IOBs: 1 out of 264 0% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 6 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 4.843ns (Maximum Frequency: 206.484MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 8.543ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file F:/clk_div3/clk_div3.vhd in Library work.Entity <clk_div3> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <clk_div3> (Architecture <behavioral>).Entity <clk_div3> analyzed. Unit <clk_div3> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <clk_div3>. Related source file is F:/clk_div3/clk_div3.vhd. Found 2-bit down counter for signal <counter1>. Found 2-bit down counter for signal <counter2>. Found 1-bit register for signal <out1_temp>. Found 1-bit register for signal <out2_temp>. Found 2 1-bit 2-to-1 multiplexers. Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Multiplexer(s).Unit <clk_div3> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# Counters : 2 2-bit down counter : 2# Registers : 2 1-bit register : 2# Multiplexers : 2 1-bit 2-to-1 multiplexer : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <clk_div3> ...Loading device for application Xst from file 'v150.nph' in environment C:/Program Files/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block clk_div3, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2s150fg456-6 Number of Slices: 5 out of 1728 0% Number of Slice Flip Flops: 6 out of 3456 0% Number of 4 input LUTs: 9 out of 3456 0% Number of bonded IOBs: 1 out of 264 0% Number of GCLKs: 1 out of 4 25% =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal | Clock buffer(FF name) | Load |-----------------------------------+------------------------+-------+clk | BUFGP | 6 |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6 Minimum period: 4.843ns (Maximum Frequency: 206.484MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 8.543ns Maximum combinational path delay: No path found=========================================================================Completed process "Synthesize".
Project Navigator Auto-Make Log File-------------------------------------
Project Navigator Auto-Make Log File-------------------------------------
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -