clk_div3.vhd

vhdl语言写的基数分频器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity clk_div3 is
port(clk:in std_logic;
     output:out std_logic);
end clk_div3;

architecture Behavioral of clk_div3 is
signal out1_temp:std_logic:='0'; 
signal out2_temp:std_logic:='0';
begin
   p1: process(clk)
	 variable counter1: integer range 0 to 3;
	 begin
       if(clk'event and clk='1')then
		     if(counter1=0)then
			      out1_temp<=not out1_temp;
			      counter1:=2;
			  elsif(counter1=2)then
					out1_temp<=not out1_temp;
					counter1:=counter1-1;
			  else
			      out1_temp<=out1_temp;
					counter1:=counter1-1;
			  end if;
		 end if;
	 end process p1;
	p2: process(clk)
	 variable counter2: integer range 0 to 3;
	 begin
       if(clk'event and clk='0')then
		     if(counter2=0)then
			      out2_temp<=not out2_temp;
			      counter2:=2;
			  elsif(counter2=2)then
					out2_temp<=not out2_temp;
					counter2:=counter2-1;
			  else
			      out2_temp<=out2_temp;
					counter2:=counter2-1;
			  end if;
		 end if;
	 end process p2;
	-- out1<=out1_temp;
	-- out2<=out2_temp;
	 output<=out1_temp or out2_temp;
end Behavioral;