liangzhu.map.eqn

在Altera的FPGA开发板上运行第一个FPGA程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
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-- (including device programming or simulation files), and any 
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-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
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-- applicable agreement for further details.
--A1L241Q is sp~reg0
--operation mode is normal

A1L241Q_lut_out = !A1L241Q;
A1L241Q = DFFEAS(A1L241Q_lut_out, A1L02, VCC, , , , , , );


--divider[0] is divider[0]
--operation mode is arithmetic

divider[0]_lut_out = !divider[0];
divider[0] = DFFEAS(divider[0]_lut_out, clk_cnt[2], VCC, , , D1_q_a[7], , , A1L02);

--A1L48 is divider[0]~281
--operation mode is arithmetic

A1L48 = CARRY(divider[0]);


--divider[1] is divider[1]
--operation mode is arithmetic

divider[1]_carry_eqn = A1L48;
divider[1]_lut_out = divider[1] $ (divider[1]_carry_eqn);
divider[1] = DFFEAS(divider[1]_lut_out, clk_cnt[2], VCC, , , D1_q_a[6], , , A1L02);

--A1L68 is divider[1]~285
--operation mode is arithmetic

A1L68 = CARRY(!A1L48 # !divider[1]);


--divider[2] is divider[2]
--operation mode is arithmetic

divider[2]_carry_eqn = A1L68;
divider[2]_lut_out = divider[2] $ (!divider[2]_carry_eqn);
divider[2] = DFFEAS(divider[2]_lut_out, clk_cnt[2], VCC, , , origin[2], , , A1L02);

--A1L88 is divider[2]~289
--operation mode is arithmetic

A1L88 = CARRY(divider[2] & (!A1L68));


--divider[3] is divider[3]
--operation mode is arithmetic

divider[3]_carry_eqn = A1L88;
divider[3]_lut_out = divider[3] $ (divider[3]_carry_eqn);
divider[3] = DFFEAS(divider[3]_lut_out, clk_cnt[2], VCC, , , D1_q_a[5], , , A1L02);

--A1L09 is divider[3]~293
--operation mode is arithmetic

A1L09 = CARRY(!A1L88 # !divider[3]);


--A1L61 is carry~89
--operation mode is normal

A1L61 = !divider[3] # !divider[2] # !divider[1] # !divider[0];


--divider[4] is divider[4]
--operation mode is arithmetic

divider[4]_carry_eqn = A1L09;
divider[4]_lut_out = divider[4] $ (!divider[4]_carry_eqn);
divider[4] = DFFEAS(divider[4]_lut_out, clk_cnt[2], VCC, , , D1_q_a[4], , , A1L02);

--A1L29 is divider[4]~297
--operation mode is arithmetic

A1L29 = CARRY(divider[4] & (!A1L09));


--divider[5] is divider[5]
--operation mode is arithmetic

divider[5]_carry_eqn = A1L29;
divider[5]_lut_out = divider[5] $ (divider[5]_carry_eqn);
divider[5] = DFFEAS(divider[5]_lut_out, clk_cnt[2], VCC, , , origin[5], , , A1L02);

--A1L49 is divider[5]~301
--operation mode is arithmetic

A1L49 = CARRY(!A1L29 # !divider[5]);


--divider[6] is divider[6]
--operation mode is arithmetic

divider[6]_carry_eqn = A1L49;
divider[6]_lut_out = divider[6] $ (!divider[6]_carry_eqn);
divider[6] = DFFEAS(divider[6]_lut_out, clk_cnt[2], VCC, , , D1_q_a[3], , , A1L02);

--A1L69 is divider[6]~305
--operation mode is arithmetic

A1L69 = CARRY(divider[6] & (!A1L49));


--divider[7] is divider[7]
--operation mode is arithmetic

divider[7]_carry_eqn = A1L69;
divider[7]_lut_out = divider[7] $ (divider[7]_carry_eqn);
divider[7] = DFFEAS(divider[7]_lut_out, clk_cnt[2], VCC, , , origin[7], , , A1L02);

--A1L89 is divider[7]~309
--operation mode is arithmetic

A1L89 = CARRY(!A1L69 # !divider[7]);


--A1L71 is carry~90
--operation mode is normal

A1L71 = !divider[7] # !divider[6] # !divider[5] # !divider[4];


--divider[8] is divider[8]
--operation mode is arithmetic

divider[8]_carry_eqn = A1L89;
divider[8]_lut_out = divider[8] $ (!divider[8]_carry_eqn);
divider[8] = DFFEAS(divider[8]_lut_out, clk_cnt[2], VCC, , , origin[8], , , A1L02);

--A1L001 is divider[8]~313
--operation mode is arithmetic

A1L001 = CARRY(divider[8] & (!A1L89));


--divider[9] is divider[9]
--operation mode is arithmetic

divider[9]_carry_eqn = A1L001;
divider[9]_lut_out = divider[9] $ (divider[9]_carry_eqn);
divider[9] = DFFEAS(divider[9]_lut_out, clk_cnt[2], VCC, , , origin[9], , , A1L02);

--A1L201 is divider[9]~317
--operation mode is arithmetic

A1L201 = CARRY(!A1L001 # !divider[9]);


--divider[10] is divider[10]
--operation mode is arithmetic

divider[10]_carry_eqn = A1L201;
divider[10]_lut_out = divider[10] $ (!divider[10]_carry_eqn);
divider[10] = DFFEAS(divider[10]_lut_out, clk_cnt[2], VCC, , , D1_q_a[2], , , A1L02);

--A1L401 is divider[10]~321
--operation mode is arithmetic

A1L401 = CARRY(divider[10] & (!A1L201));


--divider[11] is divider[11]
--operation mode is arithmetic

divider[11]_carry_eqn = A1L401;
divider[11]_lut_out = divider[11] $ (divider[11]_carry_eqn);
divider[11] = DFFEAS(divider[11]_lut_out, clk_cnt[2], VCC, , , D1_q_a[1], , , A1L02);

--A1L601 is divider[11]~325
--operation mode is arithmetic

A1L601 = CARRY(!A1L401 # !divider[11]);


--A1L81 is carry~91
--operation mode is normal

A1L81 = !divider[11] # !divider[10] # !divider[9] # !divider[8];


--divider[12] is divider[12]
--operation mode is arithmetic

divider[12]_carry_eqn = A1L601;
divider[12]_lut_out = divider[12] $ (!divider[12]_carry_eqn);
divider[12] = DFFEAS(divider[12]_lut_out, clk_cnt[2], VCC, , , D1_q_a[0], , , A1L02);

--A1L801 is divider[12]~329
--operation mode is arithmetic

A1L801 = CARRY(divider[12] & (!A1L601));


--divider[13] is divider[13]
--operation mode is normal

divider[13]_carry_eqn = A1L801;
divider[13]_lut_out = divider[13] $ (divider[13]_carry_eqn);
divider[13] = DFFEAS(divider[13]_lut_out, clk_cnt[2], VCC, , , origin[13], , , A1L02);


--A1L91 is carry~92
--operation mode is normal

A1L91 = !divider[13] # !divider[12];


--A1L02 is carry~93
--operation mode is normal

A1L02 = !A1L61 & !A1L71 & !A1L81 & !A1L91;


--clk_cnt[2] is clk_cnt[2]
--operation mode is arithmetic

clk_cnt[2]_carry_eqn = A1L52;
clk_cnt[2]_lut_out = clk_cnt[2] $ (!clk_cnt[2]_carry_eqn);
clk_cnt[2] = DFFEAS(clk_cnt[2]_lut_out, sys_clk, rst_n, , , , , , );

--A1L72 is clk_cnt[2]~169
--operation mode is arithmetic

A1L72 = CARRY(clk_cnt[2] & (!A1L52));


--D1_q_a[7] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = clk_cnt[23];
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[7] = D1_q_a[7]_PORT_A_data_out[0];


--D1_q_a[6] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[6]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[6]_PORT_A_address_reg = DFFE(D1_q_a[6]_PORT_A_address, D1_q_a[6]_clock_0, , , );
D1_q_a[6]_clock_0 = clk_cnt[23];
D1_q_a[6]_PORT_A_data_out = MEMORY(, , D1_q_a[6]_PORT_A_address_reg, , , , , , D1_q_a[6]_clock_0, , , , , );
D1_q_a[6] = D1_q_a[6]_PORT_A_data_out[0];


--origin[2] is origin[2]
--operation mode is normal

origin[2]_lut_out = A1L221 & (C1_q_a[2] # !A1L631 # !A1L531);
origin[2] = DFFEAS(origin[2]_lut_out, clk_cnt[23], VCC, , , , , , );


--D1_q_a[5] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[5]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[5]_PORT_A_address_reg = DFFE(D1_q_a[5]_PORT_A_address, D1_q_a[5]_clock_0, , , );
D1_q_a[5]_clock_0 = clk_cnt[23];
D1_q_a[5]_PORT_A_data_out = MEMORY(, , D1_q_a[5]_PORT_A_address_reg, , , , , , D1_q_a[5]_clock_0, , , , , );
D1_q_a[5] = D1_q_a[5]_PORT_A_data_out[0];


--D1_q_a[4] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[4]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[4]_PORT_A_address_reg = DFFE(D1_q_a[4]_PORT_A_address, D1_q_a[4]_clock_0, , , );
D1_q_a[4]_clock_0 = clk_cnt[23];
D1_q_a[4]_PORT_A_data_out = MEMORY(, , D1_q_a[4]_PORT_A_address_reg, , , , , , D1_q_a[4]_clock_0, , , , , );
D1_q_a[4] = D1_q_a[4]_PORT_A_data_out[0];


--origin[5] is origin[5]
--operation mode is normal

origin[5]_lut_out = A1L421 # A1L621 # A1L521 # A1L831;
origin[5] = DFFEAS(origin[5]_lut_out, clk_cnt[23], VCC, , , , , , );


--D1_q_a[3] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[3]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[3]_PORT_A_address_reg = DFFE(D1_q_a[3]_PORT_A_address, D1_q_a[3]_clock_0, , , );
D1_q_a[3]_clock_0 = clk_cnt[23];
D1_q_a[3]_PORT_A_data_out = MEMORY(, , D1_q_a[3]_PORT_A_address_reg, , , , , , D1_q_a[3]_clock_0, , , , , );
D1_q_a[3] = D1_q_a[3]_PORT_A_data_out[0];


--origin[7] is origin[7]
--operation mode is normal

origin[7]_lut_out = A1L331 & !C1_q_a[5] & !C1_q_a[4] & !C1_q_a[3];
origin[7] = DFFEAS(origin[7]_lut_out, clk_cnt[23], VCC, , , , , , );


--origin[8] is origin[8]
--operation mode is normal

origin[8]_lut_out = A1L431 & !C1_q_a[5] & !C1_q_a[1] & !high[0];
origin[8] = DFFEAS(origin[8]_lut_out, clk_cnt[23], VCC, , , , , , );


--origin[9] is origin[9]
--operation mode is normal

origin[9]_lut_out = A1L621 # A1L521 # A1L631 & A1L931;
origin[9] = DFFEAS(origin[9]_lut_out, clk_cnt[23], VCC, , , , , , );


--D1_q_a[2] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[2]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[2]_PORT_A_address_reg = DFFE(D1_q_a[2]_PORT_A_address, D1_q_a[2]_clock_0, , , );
D1_q_a[2]_clock_0 = clk_cnt[23];
D1_q_a[2]_PORT_A_data_out = MEMORY(, , D1_q_a[2]_PORT_A_address_reg, , , , , , D1_q_a[2]_clock_0, , , , , );
D1_q_a[2] = D1_q_a[2]_PORT_A_data_out[0];


--D1_q_a[1] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[1]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[1]_PORT_A_address_reg = DFFE(D1_q_a[1]_PORT_A_address, D1_q_a[1]_clock_0, , , );
D1_q_a[1]_clock_0 = clk_cnt[23];
D1_q_a[1]_PORT_A_data_out = MEMORY(, , D1_q_a[1]_PORT_A_address_reg, , , , , , D1_q_a[1]_clock_0, , , , , );
D1_q_a[1] = D1_q_a[1]_PORT_A_data_out[0];


--D1_q_a[0] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 1
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[0]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[0]_PORT_A_address_reg = DFFE(D1_q_a[0]_PORT_A_address, D1_q_a[0]_clock_0, , , );
D1_q_a[0]_clock_0 = clk_cnt[23];
D1_q_a[0]_PORT_A_data_out = MEMORY(, , D1_q_a[0]_PORT_A_address_reg, , , , , , D1_q_a[0]_clock_0, , , , , );
D1_q_a[0] = D1_q_a[0]_PORT_A_data_out[0];


--origin[13] is origin[13]
--operation mode is normal

origin[13]_lut_out = A1L221;
origin[13] = DFFEAS(origin[13]_lut_out, clk_cnt[23], VCC, , , , , , );


--clk_cnt[1] is clk_cnt[1]
--operation mode is arithmetic

clk_cnt[1]_carry_eqn = A1L32;
clk_cnt[1]_lut_out = clk_cnt[1] $ (clk_cnt[1]_carry_eqn);
clk_cnt[1] = DFFEAS(clk_cnt[1]_lut_out, sys_clk, rst_n, , , , , , );

--A1L52 is clk_cnt[1]~173
--operation mode is arithmetic

A1L52 = CARRY(!A1L32 # !clk_cnt[1]);


--clk_cnt[23] is clk_cnt[23]
--operation mode is normal

clk_cnt[23]_carry_eqn = A1L76;
clk_cnt[23]_lut_out = clk_cnt[23] $ (clk_cnt[23]_carry_eqn);
clk_cnt[23] = DFFEAS(clk_cnt[23]_lut_out, sys_clk, rst_n, , , , , , );


--high[0] is high[0]
--operation mode is normal

high[0]_lut_out = !A1L131 & !A1L87 & !A1L231 & A1L97;
high[0] = DFFEAS(high[0]_lut_out, clk_cnt[23], VCC, , , , , , );


--C1_q_a[0] is altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[0]_PORT_A_address = BUS(A1L7, A1L8, A1L87, A1L08, A1L01, A1L21, A1L18, A1L97);
C1_q_a[0]_PORT_A_address_reg = DFFE(C1_q_a[0]_PORT_A_address, C1_q_a[0]_clock_0, , , );
C1_q_a[0]_clock_0 = clk_cnt[23];
C1_q_a[0]_PORT_A_data_out = MEMORY(, , C1_q_a[0]_PORT_A_address_reg, , , , , , C1_q_a[0]_clock_0, , , , , );
C1_q_a[0] = C1_q_a[0]_PORT_A_data_out[0];


--C1_q_a[1] is altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[1]_PORT_A_address = BUS(A1L7, A1L8, A1L87, A1L08, A1L01, A1L21, A1L18, A1L97);
C1_q_a[1]_PORT_A_address_reg = DFFE(C1_q_a[1]_PORT_A_address, C1_q_a[1]_clock_0, , , );
C1_q_a[1]_clock_0 = clk_cnt[23];
C1_q_a[1]_PORT_A_data_out = MEMORY(, , C1_q_a[1]_PORT_A_address_reg, , , , , , C1_q_a[1]_clock_0, , , , , );
C1_q_a[1] = C1_q_a[1]_PORT_A_data_out[0];


--C1_q_a[2] is altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[2]_PORT_A_address = BUS(A1L7, A1L8, A1L87, A1L08, A1L01, A1L21, A1L18, A1L97);
C1_q_a[2]_PORT_A_address_reg = DFFE(C1_q_a[2]_PORT_A_address, C1_q_a[2]_clock_0, , , );
C1_q_a[2]_clock_0 = clk_cnt[23];
C1_q_a[2]_PORT_A_data_out = MEMORY(, , C1_q_a[2]_PORT_A_address_reg, , , , , , C1_q_a[2]_clock_0, , , , , );
C1_q_a[2] = C1_q_a[2]_PORT_A_data_out[0];


--C1_q_a[3] is altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[3]_PORT_A_address = BUS(A1L7, A1L8, A1L87, A1L08, A1L01, A1L21, A1L18, A1L97);
C1_q_a[3]_PORT_A_address_reg = DFFE(C1_q_a[3]_PORT_A_address, C1_q_a[3]_clock_0, , , );
C1_q_a[3]_clock_0 = clk_cnt[23];
C1_q_a[3]_PORT_A_data_out = MEMORY(, , C1_q_a[3]_PORT_A_address_reg, , , , , , C1_q_a[3]_clock_0, , , , , );
C1_q_a[3] = C1_q_a[3]_PORT_A_data_out[0];


--C1_q_a[4] is altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[4]_PORT_A_address = BUS(A1L7, A1L8, A1L87, A1L08, A1L01, A1L21, A1L18, A1L97);
C1_q_a[4]_PORT_A_address_reg = DFFE(C1_q_a[4]_PORT_A_address, C1_q_a[4]_clock_0, , , );
C1_q_a[4]_clock_0 = clk_cnt[23];
C1_q_a[4]_PORT_A_data_out = MEMORY(, , C1_q_a[4]_PORT_A_address_reg, , , , , , C1_q_a[4]_clock_0, , , , , );
C1_q_a[4] = C1_q_a[4]_PORT_A_data_out[0];


--C1_q_a[5] is altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 256, Port A Width: 1
--Port A Logical Depth: 256, Port A Logical Width: 6
--Port A Input: Registered, Port A Output: Un-registered
C1_q_a[5]_PORT_A_address = BUS(A1L7, A1L8, A1L87, A1L08, A1L01, A1L21, A1L18, A1L97);
C1_q_a[5]_PORT_A_address_reg = DFFE(C1_q_a[5]_PORT_A_address, C1_q_a[5]_clock_0, , , );
C1_q_a[5]_clock_0 = clk_cnt[23];
C1_q_a[5]_PORT_A_data_out = MEMORY(, , C1_q_a[5]_PORT_A_address_reg, , , , , , C1_q_a[5]_clock_0, , , , , );
C1_q_a[5] = C1_q_a[5]_PORT_A_data_out[0];


--A1L531 is reduce_or~664
--operation mode is normal

A1L531 = C1_q_a[3] & C1_q_a[5] & !C1_q_a[1] # !C1_q_a[3] & !C1_q_a[5] & C1_q_a[1];


--A1L631 is reduce_or~665
--operation mode is normal

A1L631 = !high[0] & !C1_q_a[0] & !C1_q_a[4];


--A1L911 is origin~152
--operation mode is normal

A1L911 = C1_q_a[1] & (!C1_q_a[0] # !C1_q_a[2]) # !C1_q_a[1] & C1_q_a[2];


--A1L721 is reduce_nor~548
--operation mode is normal

A1L721 = !high[0] & !C1_q_a[0] & !C1_q_a[1] & !C1_q_a[3];


--A1L421 is reduce_nor~0
--operation mode is normal

A1L421 = C1_q_a[4] & C1_q_a[5] & A1L721 & !C1_q_a[2];


--A1L021 is origin~153
--operation mode is normal

A1L021 = C1_q_a[5] & (high[0] # !C1_q_a[4] & !C1_q_a[3]) # !C1_q_a[5] & (C1_q_a[4] & (high[0] # !C1_q_a[3]) # !C1_q_a[4] & (C1_q_a[3]));


--A1L121 is origin~154
--operation mode is normal

A1L121 = C1_q_a[5] & !high[0] & (C1_q_a[4] # C1_q_a[3]) # !C1_q_a[5] & (C1_q_a[4] & !high[0] & C1_q_a[3] # !C1_q_a[4] & high[0] & !C1_q_a[3]);


--A1L221 is origin~155
--operation mode is normal

A1L221 = !A1L321 & (A1L021 & (A1L121) # !A1L021 & (!A1L121 # !A1L911));


--A1L621 is reduce_nor~10
--operation mode is normal

A1L621 = A1L721 & !C1_q_a[2] & !C1_q_a[4] & !C1_q_a[5];


--A1L821 is reduce_nor~549