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在Altera的FPGA开发板上运行第一个FPGA程序

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 17.462 ns
From           : sp~reg0
To             : sp
From Clock     : sys_clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'sys_clk'
Slack          : N/A
Required Time  : None
Actual Time    : 95.37 MHz ( period = 10.485 ns )
From           : altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ram_block1a0~porta_address_reg7
To             : origin[2]
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 0

Type           : Clock Hold: 'sys_clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : sp~reg0
To             : sp~reg0
From Clock     : sys_clk
To Clock       : sys_clk
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

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