liangzhu.tan.rpt

在Altera的FPGA开发板上运行第一个FPGA程序

+------------------------------+------------------------------------------+---------------+----------------------------------+------------------------------------------------------------------------------------------+-----------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; sys_clk         ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'sys_clk'                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                     ; To                                                                                       ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 95.37 MHz ( period = 10.485 ns )                    ; altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ram_block1a0~porta_address_reg0 ; origin[2]                                                                                ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.778 ns                ;
; N/A                                     ; 95.37 MHz ( period = 10.485 ns )                    ; altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ram_block1a0~porta_address_reg1 ; origin[2]                                                                                ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.778 ns                ;
; N/A                                     ; 95.37 MHz ( period = 10.485 ns )                    ; altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ram_block1a0~porta_address_reg2 ; origin[2]                                                                                ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.778 ns                ;
; N/A                                     ; 95.37 MHz ( period = 10.485 ns )                    ; altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ram_block1a0~porta_address_reg3 ; origin[2]                                                                                ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.778 ns                ;
; N/A                                     ; 95.37 MHz ( period = 10.485 ns )                    ; altsyncram:reduce_or_rtl_0|altsyncram_kcj:auto_generated|ram_block1a0~porta_address_reg4 ; origin[2]                                                                                ; sys_clk    ; sys_clk  ; None                        ; None                      ; 9.778 ns                ;