liangzhu.fit.eqn

在Altera的FPGA开发板上运行第一个FPGA程序

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--A1L871Q is sp~reg0 at LC_X14_Y8_N5
--operation mode is normal

A1L871Q_lut_out = !A1L871Q;
A1L871Q = DFFEAS(A1L871Q_lut_out, A1L82, VCC, , , , , , );


--divider[0] is divider[0] at LC_X15_Y8_N3
--operation mode is arithmetic

divider[0]_lut_out = !divider[0];
divider[0] = DFFEAS(divider[0]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[7], , , A1L82);

--A1L011 is divider[0]~281 at LC_X15_Y8_N3
--operation mode is arithmetic

A1L011_cout_0 = divider[0];
A1L011 = CARRY(A1L011_cout_0);

--A1L111 is divider[0]~281COUT1_337 at LC_X15_Y8_N3
--operation mode is arithmetic

A1L111_cout_1 = divider[0];
A1L111 = CARRY(A1L111_cout_1);


--divider[1] is divider[1] at LC_X15_Y8_N4
--operation mode is arithmetic

divider[1]_lut_out = divider[1] $ A1L011;
divider[1] = DFFEAS(divider[1]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[6], , , A1L82);

--A1L311 is divider[1]~285 at LC_X15_Y8_N4
--operation mode is arithmetic

A1L311 = CARRY(!A1L111 # !divider[1]);


--divider[2] is divider[2] at LC_X15_Y8_N5
--operation mode is arithmetic

divider[2]_carry_eqn = A1L311;
divider[2]_lut_out = divider[2] $ !divider[2]_carry_eqn;
divider[2] = DFFEAS(divider[2]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , origin[2], , , A1L82);

--A1L511 is divider[2]~289 at LC_X15_Y8_N5
--operation mode is arithmetic

A1L511_cout_0 = divider[2] & !A1L311;
A1L511 = CARRY(A1L511_cout_0);

--A1L611 is divider[2]~289COUT1_338 at LC_X15_Y8_N5
--operation mode is arithmetic

A1L611_cout_1 = divider[2] & !A1L311;
A1L611 = CARRY(A1L611_cout_1);


--divider[3] is divider[3] at LC_X15_Y8_N6
--operation mode is arithmetic

divider[3]_carry_eqn = (!A1L311 & A1L511) # (A1L311 & A1L611);
divider[3]_lut_out = divider[3] $ (divider[3]_carry_eqn);
divider[3] = DFFEAS(divider[3]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[5], , , A1L82);

--A1L811 is divider[3]~293 at LC_X15_Y8_N6
--operation mode is arithmetic

A1L811_cout_0 = !A1L511 # !divider[3];
A1L811 = CARRY(A1L811_cout_0);

--A1L911 is divider[3]~293COUT1_339 at LC_X15_Y8_N6
--operation mode is arithmetic

A1L911_cout_1 = !A1L611 # !divider[3];
A1L911 = CARRY(A1L911_cout_1);


--A1L42 is carry~89 at LC_X14_Y8_N3
--operation mode is normal

A1L42 = !divider[3] # !divider[2] # !divider[1] # !divider[0];


--divider[4] is divider[4] at LC_X15_Y8_N7
--operation mode is arithmetic

divider[4]_carry_eqn = (!A1L311 & A1L811) # (A1L311 & A1L911);
divider[4]_lut_out = divider[4] $ (!divider[4]_carry_eqn);
divider[4] = DFFEAS(divider[4]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[4], , , A1L82);

--A1L121 is divider[4]~297 at LC_X15_Y8_N7
--operation mode is arithmetic

A1L121_cout_0 = divider[4] & (!A1L811);
A1L121 = CARRY(A1L121_cout_0);

--A1L221 is divider[4]~297COUT1_340 at LC_X15_Y8_N7
--operation mode is arithmetic

A1L221_cout_1 = divider[4] & (!A1L911);
A1L221 = CARRY(A1L221_cout_1);


--divider[5] is divider[5] at LC_X15_Y8_N8
--operation mode is arithmetic

divider[5]_carry_eqn = (!A1L311 & A1L121) # (A1L311 & A1L221);
divider[5]_lut_out = divider[5] $ divider[5]_carry_eqn;
divider[5] = DFFEAS(divider[5]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , origin[5], , , A1L82);

--A1L421 is divider[5]~301 at LC_X15_Y8_N8
--operation mode is arithmetic

A1L421_cout_0 = !A1L121 # !divider[5];
A1L421 = CARRY(A1L421_cout_0);

--A1L521 is divider[5]~301COUT1_341 at LC_X15_Y8_N8
--operation mode is arithmetic

A1L521_cout_1 = !A1L221 # !divider[5];
A1L521 = CARRY(A1L521_cout_1);


--divider[6] is divider[6] at LC_X15_Y8_N9
--operation mode is arithmetic

divider[6]_carry_eqn = (!A1L311 & A1L421) # (A1L311 & A1L521);
divider[6]_lut_out = divider[6] $ (!divider[6]_carry_eqn);
divider[6] = DFFEAS(divider[6]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[3], , , A1L82);

--A1L721 is divider[6]~305 at LC_X15_Y8_N9
--operation mode is arithmetic

A1L721 = CARRY(divider[6] & (!A1L521));


--divider[7] is divider[7] at LC_X15_Y7_N0
--operation mode is arithmetic

divider[7]_carry_eqn = A1L721;
divider[7]_lut_out = divider[7] $ divider[7]_carry_eqn;
divider[7] = DFFEAS(divider[7]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , origin[7], , , A1L82);

--A1L921 is divider[7]~309 at LC_X15_Y7_N0
--operation mode is arithmetic

A1L921_cout_0 = !A1L721 # !divider[7];
A1L921 = CARRY(A1L921_cout_0);

--A1L031 is divider[7]~309COUT1_342 at LC_X15_Y7_N0
--operation mode is arithmetic

A1L031_cout_1 = !A1L721 # !divider[7];
A1L031 = CARRY(A1L031_cout_1);


--A1L52 is carry~90 at LC_X14_Y8_N6
--operation mode is normal

A1L52 = !divider[5] # !divider[7] # !divider[6] # !divider[4];


--divider[8] is divider[8] at LC_X15_Y7_N1
--operation mode is arithmetic

divider[8]_carry_eqn = (!A1L721 & A1L921) # (A1L721 & A1L031);
divider[8]_lut_out = divider[8] $ (!divider[8]_carry_eqn);
divider[8] = DFFEAS(divider[8]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , origin[8], , , A1L82);

--A1L231 is divider[8]~313 at LC_X15_Y7_N1
--operation mode is arithmetic

A1L231_cout_0 = divider[8] & (!A1L921);
A1L231 = CARRY(A1L231_cout_0);

--A1L331 is divider[8]~313COUT1_343 at LC_X15_Y7_N1
--operation mode is arithmetic

A1L331_cout_1 = divider[8] & (!A1L031);
A1L331 = CARRY(A1L331_cout_1);


--divider[9] is divider[9] at LC_X15_Y7_N2
--operation mode is arithmetic

divider[9]_carry_eqn = (!A1L721 & A1L231) # (A1L721 & A1L331);
divider[9]_lut_out = divider[9] $ (divider[9]_carry_eqn);
divider[9] = DFFEAS(divider[9]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , origin[9], , , A1L82);

--A1L531 is divider[9]~317 at LC_X15_Y7_N2
--operation mode is arithmetic

A1L531_cout_0 = !A1L231 # !divider[9];
A1L531 = CARRY(A1L531_cout_0);

--A1L631 is divider[9]~317COUT1_344 at LC_X15_Y7_N2
--operation mode is arithmetic

A1L631_cout_1 = !A1L331 # !divider[9];
A1L631 = CARRY(A1L631_cout_1);


--divider[10] is divider[10] at LC_X15_Y7_N3
--operation mode is arithmetic

divider[10]_carry_eqn = (!A1L721 & A1L531) # (A1L721 & A1L631);
divider[10]_lut_out = divider[10] $ !divider[10]_carry_eqn;
divider[10] = DFFEAS(divider[10]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[2], , , A1L82);

--A1L831 is divider[10]~321 at LC_X15_Y7_N3
--operation mode is arithmetic

A1L831_cout_0 = divider[10] & !A1L531;
A1L831 = CARRY(A1L831_cout_0);

--A1L931 is divider[10]~321COUT1_345 at LC_X15_Y7_N3
--operation mode is arithmetic

A1L931_cout_1 = divider[10] & !A1L631;
A1L931 = CARRY(A1L931_cout_1);


--divider[11] is divider[11] at LC_X15_Y7_N4
--operation mode is arithmetic

divider[11]_carry_eqn = (!A1L721 & A1L831) # (A1L721 & A1L931);
divider[11]_lut_out = divider[11] $ divider[11]_carry_eqn;
divider[11] = DFFEAS(divider[11]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[1], , , A1L82);

--A1L141 is divider[11]~325 at LC_X15_Y7_N4
--operation mode is arithmetic

A1L141 = CARRY(!A1L931 # !divider[11]);


--A1L62 is carry~91 at LC_X14_Y8_N8
--operation mode is normal

A1L62 = !divider[9] # !divider[8] # !divider[11] # !divider[10];


--divider[12] is divider[12] at LC_X15_Y7_N5
--operation mode is arithmetic

divider[12]_carry_eqn = A1L141;
divider[12]_lut_out = divider[12] $ !divider[12]_carry_eqn;
divider[12] = DFFEAS(divider[12]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , D1_q_a[0], , , A1L82);

--A1L341 is divider[12]~329 at LC_X15_Y7_N5
--operation mode is arithmetic

A1L341_cout_0 = divider[12] & !A1L141;
A1L341 = CARRY(A1L341_cout_0);

--A1L441 is divider[12]~329COUT1_346 at LC_X15_Y7_N5
--operation mode is arithmetic

A1L441_cout_1 = divider[12] & !A1L141;
A1L441 = CARRY(A1L441_cout_1);


--divider[13] is divider[13] at LC_X15_Y7_N6
--operation mode is normal

divider[13]_carry_eqn = (!A1L141 & A1L341) # (A1L141 & A1L441);
divider[13]_lut_out = divider[13]_carry_eqn $ divider[13];
divider[13] = DFFEAS(divider[13]_lut_out, GLOBAL(clk_cnt[2]), VCC, , , origin[13], , , A1L82);


--A1L72 is carry~92 at LC_X14_Y8_N7
--operation mode is normal

A1L72 = !divider[12] # !divider[13];


--A1L82 is carry~93 at LC_X14_Y8_N9
--operation mode is normal

A1L82 = !A1L52 & !A1L42 & !A1L72 & !A1L62;


--clk_cnt[2] is clk_cnt[2] at LC_X8_Y12_N5
--operation mode is arithmetic

clk_cnt[2]_carry_eqn = A1L43;
clk_cnt[2]_lut_out = clk_cnt[2] $ !clk_cnt[2]_carry_eqn;
clk_cnt[2] = DFFEAS(clk_cnt[2]_lut_out, GLOBAL(sys_clk), GLOBAL(rst_n), , , , , , );

--A1L63 is clk_cnt[2]~169 at LC_X8_Y12_N5
--operation mode is arithmetic

A1L63_cout_0 = clk_cnt[2] & !A1L43;
A1L63 = CARRY(A1L63_cout_0);

--A1L73 is clk_cnt[2]~169COUT1_266 at LC_X8_Y12_N5
--operation mode is arithmetic

A1L73_cout_1 = clk_cnt[2] & !A1L43;
A1L73 = CARRY(A1L73_cout_1);


--D1_q_a[7] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[7] at M4K_X17_Y8
--RAM Block Operation Mode: ROM
--Port A Depth: 128, Port A Width: 8
--Port A Logical Depth: 128, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[7] = D1_q_a[7]_PORT_A_data_out[0];

--D1_q_a[0] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[0] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[0] = D1_q_a[7]_PORT_A_data_out[7];

--D1_q_a[1] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[1] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[1] = D1_q_a[7]_PORT_A_data_out[6];

--D1_q_a[2] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[2] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[2] = D1_q_a[7]_PORT_A_data_out[5];

--D1_q_a[3] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[3] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[3] = D1_q_a[7]_PORT_A_data_out[4];

--D1_q_a[4] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[4] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[4] = D1_q_a[7]_PORT_A_data_out[3];

--D1_q_a[5] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[5] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[5] = D1_q_a[7]_PORT_A_data_out[2];

--D1_q_a[6] is altsyncram:reduce_or_rtl_1|altsyncram_lcj:auto_generated|q_a[6] at M4K_X17_Y8
D1_q_a[7]_PORT_A_address = BUS(high[0], C1_q_a[0], C1_q_a[1], C1_q_a[2], C1_q_a[3], C1_q_a[4], C1_q_a[5]);
D1_q_a[7]_PORT_A_address_reg = DFFE(D1_q_a[7]_PORT_A_address, D1_q_a[7]_clock_0, , , );
D1_q_a[7]_clock_0 = GLOBAL(clk_cnt[23]);
D1_q_a[7]_PORT_A_data_out = MEMORY(, , D1_q_a[7]_PORT_A_address_reg, , , , , , D1_q_a[7]_clock_0, , , , , );
D1_q_a[6] = D1_q_a[7]_PORT_A_data_out[1];


--origin[2] is origin[2] at LC_X15_Y9_N1
--operation mode is normal

origin[2]_lut_out = A1L851 & (C1_q_a[2] # !A1L171 # !A1L271);
origin[2] = DFFEAS(origin[2]_lut_out, GLOBAL(clk_cnt[23]), VCC, , , , , , );


--origin[5] is origin[5] at LC_X15_Y9_N8
--operation mode is normal

origin[5]_lut_out = A1L261 # A1L061 # A1L161 # A1L471;
origin[5] = DFFEAS(origin[5]_lut_out, GLOBAL(clk_cnt[23]), VCC, , , , , , );


--origin[7] is origin[7] at LC_X14_Y9_N7
--operation mode is normal

origin[7]_lut_out = !C1_q_a[3] & A1L961 & !C1_q_a[4] & !C1_q_a[5];
origin[7] = DFFEAS(origin[7]_lut_out, GLOBAL(clk_cnt[23]), VCC, , , , , , );


--origin[8] is origin[8] at LC_X16_Y9_N9
--operation mode is normal

origin[8]_lut_out = !C1_q_a[1] & !high[0] & A1L071 & !C1_q_a[5];
origin[8] = DFFEAS(origin[8]_lut_out, GLOBAL(clk_cnt[23]), VCC, , , , , , );


--origin[9] is origin[9] at LC_X16_Y9_N5
--operation mode is normal

origin[9]_lut_out = A1L261 # A1L161 # A1L271 & A1L571;
origin[9] = DFFEAS(origin[9]_lut_out, GLOBAL(clk_cnt[23]), VCC, , , , , , );