exe.syr

用VHDL 编写的一个16位的cpu 设计方案

#      LDCP                        : 8
#      LDE                         : 104
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 64
#      IBUF                        : 29
#      OBUF                        : 35
=========================================================================

Device utilization summary:
---------------------------

Selected Device : v200pq240-4 

 Number of Slices:                     163  out of   2352     6%  
 Number of Slice Flip Flops:           112  out of   4704     2%  
 Number of 4 input LUTs:               284  out of   4704     6%  
 Number of bonded IOBs:                 64  out of    170    37%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
ex                                 | BUFGP                  | 80    |
_n0096(_n00961:O)                  | NONE(*)(mdrout_1)      | 24    |
u1__n0002(u1__n00021:O)            | NONE(*)(u1_output_5)   | 8     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 9.983ns (Maximum Frequency: 100.168MHz)
   Minimum input arrival time before clock: 15.205ns
   Maximum output required time after clock: 20.141ns
   Maximum combinational path delay: 23.053ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'ex'
Delay:               9.983ns (Levels of Logic = 5)
  Source:            reg_0_7 (LATCH)
  Destination:       input1_7 (LATCH)
  Source Clock:      ex falling
  Destination Clock: ex falling

  Data Path: reg_0_7 to input1_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              3   1.509   1.628  reg_0_7 (reg_0_7)
     LUT3_L:I1->LO         1   0.738   0.000  Mmux__n0001_inst_lut3_281 (Mmux__n0001__net49)
     MUXF5:I0->O           1   0.562   0.000  Mmux__n0001_inst_mux_f5_14 (Mmux__n0001__net51)
     MUXF6:I0->O           3   0.412   1.628  Mmux__n0001_inst_mux_f6_7 (_n0001<7>)
     LUT4:I3->O            1   0.738   1.265  Mmux__n0097_Result<7>15 (CHOICE115)
     LUT4_L:I0->LO         1   0.738   0.000  Mmux__n0097_Result<7>58 (_n0097<7>)
     LDE:D                     0.765          input1_7
    ----------------------------------------
    Total                      9.983ns (5.462ns logic, 4.521ns route)
                                       (54.7% logic, 45.3% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock '_n00961:O'
Delay:               4.486ns (Levels of Logic = 1)
  Source:            mar_15 (LATCH)
  Destination:       mar_15 (LATCH)
  Source Clock:      _n00961:O falling
  Destination Clock: _n00961:O falling

  Data Path: mar_15 to mar_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  mar_15 (mar_15)
     LUT3:I1->O            1   0.738   0.000  Mmux__n0099_Result1 (_n0099)
     LDE:D                     0.765          mar_15
    ----------------------------------------
    Total                      4.486ns (3.012ns logic, 1.474ns route)
                                       (67.1% logic, 32.9% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'ex'
Offset:              14.551ns (Levels of Logic = 5)
  Source:            r1<0> (PAD)
  Destination:       reg_6_5 (LATCH)
  Destination Clock: ex falling

  Data Path: r1<0> to reg_6_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            48   0.989   5.060  r1_0_IBUF (r1_0_IBUF)
     LUT3:I2->O            1   0.738   1.265  Ker586420_SW0_SW0 (N8444)
     LUT4:I0->O            1   0.738   1.265  Ker586420_SW0 (N8356)
     LUT2:I1->O            8   0.738   2.255  Ker586420 (N6952)
     LUT4:I0->O            1   0.738   0.000  Mmux__n0092_Result<0>1 (_n0092<0>)
     LDE:D                     0.765          reg_4_0
    ----------------------------------------
    Total                     14.551ns (4.706ns logic, 9.845ns route)
                                       (32.3% logic, 67.7% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock '_n00961:O'
Offset:              11.865ns (Levels of Logic = 3)
  Source:            opcode<3> (PAD)
  Destination:       mar_15 (LATCH)
  Destination Clock: _n00961:O falling

  Data Path: opcode<3> to mar_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            57   0.989   5.555  opcode_3_IBUF (opcode_3_IBUF)
     LUT4:I0->O           16   0.738   3.080  _n0136 (_n0136)
     LUT3:I0->O            1   0.738   0.000  Mmux__n0100_Result1 (_n0100)
     LDE:D                     0.765          mar_14
    ----------------------------------------
    Total                     11.865ns (3.230ns logic, 8.635ns route)
                                       (27.2% logic, 72.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'u1__n00021:O'
Offset:              15.205ns (Levels of Logic = 12)
  Source:            opcode<2> (PAD)
  Destination:       u1_output_7 (LATCH)
  Destination Clock: u1__n00021:O falling

  Data Path: opcode<2> to u1_output_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            57   0.989   5.555  opcode_2_IBUF (opcode_2_IBUF)
     LUT4:I1->O            9   0.738   2.332  u1__n00061 (u1__n0006)
     LUT3:I2->O            1   0.738   0.000  u1_Maddsub__n0007_inst_lut3_641 (u1_Maddsub__n0007_inst_lut3_64)
     MUXCY:S->O            1   0.842   0.000  u1_Maddsub__n0007_inst_cy_0 (u1_Maddsub__n0007_inst_cy_0)
     MUXCY:CI->O           1   0.057   0.000  u1_Maddsub__n0007_inst_cy_1 (u1_Maddsub__n0007_inst_cy_1)
     MUXCY:CI->O           1   0.057   0.000  u1_Maddsub__n0007_inst_cy_2 (u1_Maddsub__n0007_inst_cy_2)
     MUXCY:CI->O           1   0.057   0.000  u1_Maddsub__n0007_inst_cy_3 (u1_Maddsub__n0007_inst_cy_3)
     MUXCY:CI->O           1   0.057   0.000  u1_Maddsub__n0007_inst_cy_4 (u1_Maddsub__n0007_inst_cy_4)
     MUXCY:CI->O           1   0.057   0.000  u1_Maddsub__n0007_inst_cy_5 (u1_Maddsub__n0007_inst_cy_5)
     MUXCY:CI->O           0   0.057   0.000  u1_Maddsub__n0007_inst_cy_6 (u1_Maddsub__n0007_inst_cy_6)
     XORCY:CI->O           3   0.538   1.628  u1_Maddsub__n0007_inst_sum_7 (u1__n0012<15>)
     LUT3:I1->O            1   0.738   0.000  u1_Mmux__n0004_Result<7>1 (u1__n0004<7>)
     LDCP:D                    0.765          u1_output_7
    ----------------------------------------
    Total                     15.205ns (5.690ns logic, 9.515ns route)
                                       (37.4% logic, 62.6% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'ex'
Offset:              20.141ns (Levels of Logic = 8)
  Source:            reg_0_0 (LATCH)
  Destination:       rz (PAD)
  Source Clock:      ex falling

  Data Path: reg_0_0 to rz
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              3   1.509   1.628  reg_0_0 (reg_0_0)
     LUT3_L:I1->LO         1   0.738   0.000  Mmux__n0001_inst_lut3_01 (Mmux__n0001__net0)
     MUXF5:I0->O           1   0.562   0.000  Mmux__n0001_inst_mux_f5_0 (Mmux__n0001__net2)
     MUXF6:I0->O           3   0.412   1.628  Mmux__n0001_inst_mux_f6_0 (_n0001<0>)
     LUT4:I0->O            1   0.738   1.265  rz34 (CHOICE102)
     LUT4:I3->O            1   0.738   1.265  rz60_SW0 (N8327)
     LUT4:I3->O            1   0.738   1.265  rz60 (CHOICE105)
     LUT4:I0->O            1   0.738   1.265  rz94 (rz_OBUF)
     OBUF:I->O                 5.652          rz_OBUF (rz)
    ----------------------------------------
    Total                     20.141ns (11.825ns logic, 8.316ns route)
                                       (58.7% logic, 41.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock '_n00961:O'
Offset:              8.635ns (Levels of Logic = 1)
  Source:            mar_15 (LATCH)
  Destination:       mar<15> (PAD)
  Source Clock:      _n00961:O falling

  Data Path: mar_15 to mar<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LDE:G->Q              2   1.509   1.474  mar_15 (mar_15)
     OBUF:I->O                 5.652          mar_15_OBUF (mar<15>)
    ----------------------------------------
    Total                      8.635ns (7.161ns logic, 1.474ns route)
                                       (82.9% logic, 17.1% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               23.053ns (Levels of Logic = 9)
  Source:            r1<0> (PAD)
  Destination:       rz (PAD)

  Data Path: r1<0> to rz
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            48   0.989   5.060  r1_0_IBUF (r1_0_IBUF)
     LUT3_L:I0->LO         1   0.738   0.000  Mmux__n0001_inst_lut3_41 (Mmux__n0001__net7)
     MUXF5:I0->O           1   0.562   0.000  Mmux__n0001_inst_mux_f5_2 (Mmux__n0001__net9)
     MUXF6:I0->O           3   0.412   1.628  Mmux__n0001_inst_mux_f6_1 (_n0001<1>)
     LUT4:I1->O            1   0.738   1.265  rz34 (CHOICE102)
     LUT4:I3->O            1   0.738   1.265  rz60_SW0 (N8327)
     LUT4:I3->O            1   0.738   1.265  rz60 (CHOICE105)
     LUT4:I0->O            1   0.738   1.265  rz94 (rz_OBUF)
     OBUF:I->O                 5.652          rz_OBUF (rz)
    ----------------------------------------
    Total                     23.053ns (11.305ns logic, 11.748ns route)
                                       (49.0% logic, 51.0% route)

=========================================================================
CPU : 4.28 / 4.76 s | Elapsed : 4.00 / 4.00 s
 
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Total memory usage is 62144 kilobytes