rt_window_monitor.v

来自「FPGA之间的LVDS传输」· Verilog 代码 · 共 883 行 · 第 1/2 页

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			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	COMPARE_MINUS1:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b1;
			UD1			<= 1'b1;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	RECORD_0_1:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b1;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;	//ERRORS
			end
	
	RECORD_1_1:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b1;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b1;	//ERROR FREE
			end
	
	DEC_1_1:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b1;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	WAIT7_1:	begin
			COUNT0			<= 1'b1;
			UD0			<= 1'b1;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	COMPARE_MINUS2:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b1;
			UD1			<= 1'b1;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	RECORD_0_2:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b1;	//-2
			STATUS			<= 1'b0;	//ERRORS
			end
	
	RECORD_1_2:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b1;	//-2
			STATUS			<= 1'b1;	//ERROR FREE
			end
	
	INC_3:		begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b1;
			UD1			<= 1'b1;	
			INC_MONITOR		<= 1'b1;
			ICE_MONITOR		<= 1'b1;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	WAIT7_2:	begin
			COUNT0			<= 1'b1;
			UD0			<= 1'b1;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	COMPARE_PLUS1:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b1;
			UD1			<= 1'b1;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	RECORD_0_3:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b1;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;	//ERRORS
			end
	
	RECORD_1_3:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b1;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b1;	//ERROR FREE
			end
	
	INC_1:		begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b1;
			ICE_MONITOR		<= 1'b1;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	WAIT7_3:	begin
			COUNT0			<= 1'b1;
			UD0			<= 1'b1;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	COMPARE_PLUS2:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b1;
			UD1			<= 1'b1;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	RECORD_0_4:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b1;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	RECORD_1_4:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b1;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b1;
			end
	
	IDLE:		begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	BEGIN_ADJUST:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	INC_ALL:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b1;
			ICE_MONITOR		<= 1'b1;
			INC_DATABUS		<= 1'b1;
			ICE_DATABUS		<= 1'b1;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	DEC_ALL:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b1;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b1;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	DEC_2:		begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b1;
			UD1			<= 1'b1;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b1;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	DONE:		begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	default:	begin
			COUNT0			<= 1'b0;
			UD0			<= 1'b0;
			COUNT1			<= 1'b0;
			UD1			<= 1'b0;	
			INC_MONITOR		<= 1'b0;
			ICE_MONITOR		<= 1'b0;
			INC_DATABUS		<= 1'b0;
			ICE_DATABUS		<= 1'b0;	
			STORE_STATUS[0]		<= 1'b0;	//+2
			STORE_STATUS[1]		<= 1'b0;	//+1
			STORE_STATUS[2]		<= 1'b0;	//0
			STORE_STATUS[3]		<= 1'b0;	//-1
			STORE_STATUS[4]		<= 1'b0;	//-2
			STATUS			<= 1'b0;
			end
	
	endcase
end
	
endmodule
12

rt_window_monitor.v - 源码说明

本页面展示了「FPGA之间的LVDS传输」中的 rt_window_monitor.v 源码文件，采用 Verilog 编程语言编写，共 883 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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