📄 ddr_6to1_16chan_rt_rx_map.mrp
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Section 5 - Removed Logic-------------------------The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections. If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented. This
indentation will be repeated as a chain of related logic is removed.To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).The signal "U_FIFO/full" is sourceless and has been removed.The signal "U_FIFO/empty" is sourceless and has been removed.The signal "U_FIFO/almost_full" is sourceless and has been removed.The signal "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not0001" is
sourceless and has been removed. Sourceless block "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i" (FF)
removed.The signal "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000" is
sourceless and has been removed.The signal "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/wr_rst_d1" is sourceless and
has been removed. Sourceless block
"U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011" (ROM)
removed. Sourceless block
"U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000144" (ROM)
removed.The signal "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux00008" is
sourceless and has been removed.The signal "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000035"
is sourceless and has been removed.The signal "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000112"
is sourceless and has been removed.Unused block "U_FIFO/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i" (FF) removed.Unused block
"U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000112" (ROM)
removed.Unused block "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000035"
(ROM) removed.Unused block "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux00008"
(ROM) removed.Unused block "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i" (FF) removed.Unused block "U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/wr_rst_d1" (FF) removed.Unused block "U_FIFO/GND" (ZERO) removed.Unused block "U_FIFO/VCC" (ONE) removed.Optimized Block(s):TYPE BLOCKGND U_FIFO/BU2/XST_GNDVCC U_FIFO/BU2/XST_VCCGND XST_GNDVCC XST_VCCTo enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.Section 6 - IOB Properties--------------------------+----------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+----------------------------------------------------------------------------------------------------------------------------------------+| BITSLIP_PAD | IOB | INPUT | LVCMOS25 | | | | | || CLK200 | IOB | INPUT | LVCMOS25 | | | | | || CLOCK_RX_N | IOB | INPUT | See master | | | | | || CLOCK_RX_P | IOB | INPUT | LVDS_25 | | | | | FIXED || DATA_RX_FIFO<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<8> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<9> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<10> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<11> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<12> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<13> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<14> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<15> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<16> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<17> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<18> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<19> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<20> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<21> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<22> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<23> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<24> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<25> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<26> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<27> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<28> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<29> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<30> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<31> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<32> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<33> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<34> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<35> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<36> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<37> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<38> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<39> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<40> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<41> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<42> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<43> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<44> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<45> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<46> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<47> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<48> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<49> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<50> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<51> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<52> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<53> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_RX_FIFO<54> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | |⌨️ 快捷键说明
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