ddr_6to1_16chan_rt_rx_map.mrp

来自「FPGA之间的LVDS传输」· MRP 代码 · 共 630 行 · 第 1/5 页

MRP
630 行
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WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_CNTL>:<IODELAY_IODELAY>.  When DELAY_SRC is not DATAIN
   programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_00>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_01>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_10>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_02>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_11>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_03>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_12>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_04>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_13>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_05>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_14>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_06>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_15>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_07>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_08>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_09>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_MON_CNTL>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_00>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_01>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_10>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_02>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_11>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_03>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_12>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_04>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_13>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_05>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_14>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_06>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_15>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_07>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_16>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_08>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_MON_09>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_CNTL>:<ISERDES_ISERDES>.  Useless CE2 input pin. With
   NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_00>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_01>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_10>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_02>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_11>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_03>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_12>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_04>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_13>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_05>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_14>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_06>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_15>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_07>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_08>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<IODELAY_RX_DATA_09>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<ISERDES_CLOCK_RX>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
   1.050 Volts)INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).INFO:Pack:1650 - Map created a placed design.Section 4 - Removed Logic Summary---------------------------------  11 block(s) removed   4 block(s) optimized away   9 signal(s) removed
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ddr_6to1_16chan_rt_rx_map.mrp - 源码说明

本页面展示了「FPGA之间的LVDS传输」中的 ddr_6to1_16chan_rt_rx_map.mrp 源码文件，采用 MRP 编程语言编写，共 630 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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