ddr_6to1_16chan_rt_rx_map.mrp

FPGA之间的LVDS传输

Release 10.1.02 Map K.37 (nt)
Xilinx Mapping Report File for Design 'DDR_6TO1_16CHAN_RT_RX'

Design Information
------------------
Command Line   : map -ise E:/ISEworks/LVDS/LVDS_4to1/xapp860.ise -intstyle ise -p xc5vsx50t-ff1136-1 -w -logic_opt off
-ol high -t 1 -cm area -pr off -k 6 -lc off -power off -o DDR_6TO1_16CHAN_RT_RX_map.ncd DDR_6TO1_16CHAN_RT_RX.ngd
DDR_6TO1_16CHAN_RT_RX.pcf 
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Sun Aug 24 13:05:33 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:   72
Slice Logic Utilization:
  Number of Slice Registers:                   502 out of  32,640    1%
    Number used as Flip Flops:                 502
  Number of Slice LUTs:                        718 out of  32,640    2%
    Number used as logic:                      714 out of  32,640    2%
      Number using O6 output only:             714
    Number used as Memory:                       4 out of  12,480    1%
      Number used as Shift Register:             4
        Number using O6 output only:             4

Slice Logic Distribution:
  Number of occupied Slices:                   314 out of   8,160    3%
  Number of LUT Flip Flop pairs used:          865
    Number with an unused Flip Flop:           363 out of     865   41%
    Number with an unused LUT:                 147 out of     865   16%
    Number of fully used LUT-FF pairs:         355 out of     865   41%
    Number of unique control sets:              40
    Number of slice register sites lost
      to control set restrictions:              90 out of  32,640    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       215 out of     480   44%

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                       1 out of     132    1%
    Number using BlockRAM only:                  1
    Total primitives used:
      Number of 36k BlockRAM used:               1
    Total Memory used (KB):                     36 out of   4,752    1%
  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%
    Number used as BUFGs:                        2
  Number of BUFIOs:                              1 out of      56    1%
  Number of BUFRs:                               1 out of      24    4%
  Number of ISERDESs:                           34

Peak Memory Usage:  399 MB
Total REAL time to MAP completion:  1 mins 46 secs 
Total CPU time to MAP completion:   1 mins 43 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network RXCLK has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 9
   more times for the following (max. 5 shown):
   TAP_CLK<5>,
   TAP_CLK<4>,
   TAP_CLK<3>,
   TAP_CLK<2>,
   TAP_CLK<1>
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_00>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_01>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_10>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_02>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_11>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_03>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_12>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_04>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_13>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_05>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_14>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_06>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_15>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_07>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_08>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.
WARNING:PhysDesignRules:1325 - Dangling pins on block:<ISERDES_RX_DATA_09>:<ISERDES_ISERDES>.  Useless CE2 input pin.
   With NUM_CE set 1 the CE2 input pin is being ignored.