cmi译码.txt

一个用VHDL编写的一个cmi解码编码程序。可以对数据进行编码技术。加密。

LIBRARY  IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY CMI IS
   PORT( CLK :IN STD_LOGIC;
         KEY : IN STD_LOGIC_VECTOR( 7 DOWNTO 0);
          CMIIN : IN STD_LOGIC;
          CMIOUT: OUT STD_LOGIC;
          SOUT: OUT STD_LOGIC);
END CMI;
ARCHITECTURE  BEHAVE OF CMI IS
  SIGNAL SIN : STD_LOGIC;
  SIGNAL SCOUNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
  SIGNAL CMI_TEMP :STD_LOGIC;
  SIGNAL CMI_OUT :STD_LOGIC;
  SIGNAL S1,S2:STD_LOGIC;
 BEGIN
PROCESS(CLK)
   BEGIN
     IF(CLK'EVENT AND CLK='1')THEN
        SCOUNT<=SCOUNT+1;
      CASE (SCOUNT) IS
          WHEN "000"=>SIN<=KEY(7);
          WHEN "001"=>SIN<=KEY(6);
          WHEN "010"=>SIN<=KEY(5);
          WHEN "011"=>SIN<=KEY(4);
          WHEN "100"=>SIN<=KEY(3);
          WHEN "101"=>SIN<=KEY(2);
          WHEN "110"=>SIN<=KEY(1);
          WHEN "111"=>SIN<=KEY(0);
          WHEN OTHERS=> SIN<='0';
     END CASE;
  CMI_TEMP<= NOT CMI_TEMP;
  END IF;
END PROCESS; 
PROCESS(CLK,SCOUNT)
    BEGIN
      IF(SIN='1') THEN
          CMIOUT<=CMI_TEMP;
      ELSE
          CMIOUT<=NOT CLK;
      END IF;
 END PROCESS;
 PROCESS(CLK)
   BEGIN
        IF(CLK'EVENT AND CLK='1') THEN
        S1<=CMIIN;
        END IF;
        IF(CLK'EVENT AND CLK='0') THEN
        S2<=CMIIN;
        END IF;
 END PROCESS;
PROCESS(CLK)
  BEGIN
     IF(CLK'EVENT AND CLK='0')  THEN
        SOUT<=NOT (S1 XOR S2);
   END IF;
      END PROCESS;
END BEHAVE;