testbench.vhd.bak

16位的移位寄存器

library IEEE;
use IEEE.std_logic_1164.all;
entity testshift is
end testshift;
architecture testbench of testshift is

component shift_register is
port (Clk : in std_logic;
      Rst : in std_logic;
     Enable : in std_logic;
       Addr : in std_logic_vector(3 downto 0);
    Data_in : in std_logic_vector(7 downto 0);
   Data_out : out std_logic_vector(7 downto 0));
end component;

signal Clk, Rst, Enable: std_logic;
signal Data_in, Data_out: std_logic_vector(7 downto 0);
signal Addr: std_logic_vector(3 downto 0);
constant ClockPeriod : TIME := 50 ns;

begin
shi: shift_register port map (Clk => Clk, Rst => Rst, Enable => Enable, Addr => Addr, Data_in => Data_in, Data_out => Data_out);

process begin
Clk <= '1';
wait for ClockPeriod / 2;
Clk <= '0';
wait for ClockPeriod / 2;
end process;

process begin
Addr <= "0000";
Rst <= '1';
Enable <= '1';
Data_in <= "11100000";
wait for 100 ns;
Rst <= '0';
Enable <= '1';
wait for 100 ns;
Rst <= '0';
Enable <= '1';
Data_in <= "00010001";
wait for 100 ns;
Data_in <= "00010101";

wait for 100 ns;
Data_in <= "00010101";

wait for 100 ns;
end process;

end architecture testbench;