uart_tr.tan.qmsg

Verilog编写的简单异步串口 完全原创

{ "Info" "ITDB_FULL_TCO_RESULT" "clock txd always2~0 19.900 ns register " "Info: tco from clock \"clock\" to destination pin \"txd\" through register \"always2~0\" is 19.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 8.600 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to source register is 8.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 66 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 66; CLK Node = 'clock'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { clock } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk2 2 REG LC2_A17 11 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC2_A17; Fanout = 11; REG Node = 'clk2'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "3.600 ns" { clock clk2 } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.000 ns) 8.600 ns always2~0 3 REG LC1_A21 1 " "Info: 3: + IC(2.200 ns) + CELL(0.000 ns) = 8.600 ns; Loc. = LC1_A21; Fanout = 1; REG Node = 'always2~0'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "2.200 ns" { clk2 always2~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 45.35 % " "Info: Total cell delay = 3.900 ns ( 45.35 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.700 ns 54.65 % " "Info: Total interconnect delay = 4.700 ns ( 54.65 % )" {  } {  } 0}  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "8.600 ns" { clock clk2 always2~0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clock clock~out clk2 always2~0 } { 0.000ns 0.000ns 2.500ns 2.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.200 ns + Longest register pin " "Info: + Longest register to pin delay is 10.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns always2~0 1 REG LC1_A21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_A21; Fanout = 1; REG Node = 'always2~0'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { always2~0 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(6.100 ns) 10.200 ns txd 2 PIN PIN_54 0 " "Info: 2: + IC(4.100 ns) + CELL(6.100 ns) = 10.200 ns; Loc. = PIN_54; Fanout = 0; PIN Node = 'txd'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "10.200 ns" { always2~0 txd } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 4 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.100 ns 59.80 % " "Info: Total cell delay = 6.100 ns ( 59.80 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.100 ns 40.20 % " "Info: Total interconnect delay = 4.100 ns ( 40.20 % )" {  } {  } 0}  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "10.200 ns" { always2~0 txd } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "10.200 ns" { always2~0 txd } { 0.000ns 4.100ns } { 0.000ns 6.100ns } } }  } 0}  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "8.600 ns" { clock clk2 always2~0 } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "8.600 ns" { clock clock~out clk2 always2~0 } { 0.000ns 0.000ns 2.500ns 2.200ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "10.200 ns" { always2~0 txd } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "10.200 ns" { always2~0 txd } { 0.000ns 4.100ns } { 0.000ns 6.100ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "r_temp\[6\] rxd clock 3.600 ns register " "Info: th for register \"r_temp\[6\]\" (data pin = \"rxd\", clock pin = \"clock\") is 3.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 11.000 ns + Longest register " "Info: + Longest clock path from clock \"clock\" to destination register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 66 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 66; CLK Node = 'clock'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { clock } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 3 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk 2 REG LC1_B14 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B14; Fanout = 26; REG Node = 'clk'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "3.600 ns" { clock clk } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns r_temp\[6\] 3 REG LC3_A9 10 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC3_A9; Fanout = 10; REG Node = 'r_temp\[6\]'" {  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "4.600 ns" { clk r_temp[6] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" {  } {  } 0}  } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/