📄 uart_tr.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk2 " "Info: Detected ripple clock \"clk2\" as buffer" { } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } { "d:/program files/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "clk " "Info: Detected ripple clock \"clk\" as buffer" { } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 22 -1 0 } } { "d:/program files/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clock register num_clk2\[1\] register num_clk2\[31\] 43.67 MHz 22.9 ns Internal " "Info: Clock \"clock\" has Internal fmax of 43.67 MHz between source register \"num_clk2\[1\]\" and destination register \"num_clk2\[31\]\" (period= 22.9 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.300 ns + Longest register register " "Info: + Longest register to register delay is 19.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns num_clk2\[1\] 1 REG LC1_C14 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C14; Fanout = 3; REG Node = 'num_clk2\[1\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { num_clk2[1] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.200 ns) 3.500 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC2_C13 2 " "Info: 2: + IC(2.300 ns) + CELL(1.200 ns) = 3.500 ns; Loc. = LC2_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "3.500 ns" { num_clk2[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 3.800 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC3_C13 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC3_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.100 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC4_C13 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC4_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.400 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC5_C13 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC5_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.700 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC6_C13 2 " "Info: 6: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC6_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.000 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 7 COMB LC7_C13 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC7_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.300 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 8 COMB LC8_C13 2 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 5.300 ns; Loc. = LC8_C13; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.300 ns) 6.400 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 9 COMB LC1_C15 2 " "Info: 9: + IC(0.800 ns) + CELL(0.300 ns) = 6.400 ns; Loc. = LC1_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "1.100 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 6.700 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 10 COMB LC2_C15 2 " "Info: 10: + IC(0.000 ns) + CELL(0.300 ns) = 6.700 ns; Loc. = LC2_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.000 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 11 COMB LC3_C15 2 " "Info: 11: + IC(0.000 ns) + CELL(0.300 ns) = 7.000 ns; Loc. = LC3_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.300 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 12 COMB LC4_C15 2 " "Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 7.300 ns; Loc. = LC4_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.600 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 13 COMB LC5_C15 2 " "Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 7.600 ns; Loc. = LC5_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.900 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 14 COMB LC6_C15 2 " "Info: 14: + IC(0.000 ns) + CELL(0.300 ns) = 7.900 ns; Loc. = LC6_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 8.200 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 15 COMB LC7_C15 2 " "Info: 15: + IC(0.000 ns) + CELL(0.300 ns) = 8.200 ns; Loc. = LC7_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 8.500 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\] 16 COMB LC8_C15 2 " "Info: 16: + IC(0.000 ns) + CELL(0.300 ns) = 8.500 ns; Loc. = LC8_C15; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[15\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.300 ns) 9.600 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\] 17 COMB LC1_C17 2 " "Info: 17: + IC(0.800 ns) + CELL(0.300 ns) = 9.600 ns; Loc. = LC1_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[16\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "1.100 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 9.900 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\] 18 COMB LC2_C17 2 " "Info: 18: + IC(0.000 ns) + CELL(0.300 ns) = 9.900 ns; Loc. = LC2_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[17\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[17] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 10.200 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\] 19 COMB LC3_C17 2 " "Info: 19: + IC(0.000 ns) + CELL(0.300 ns) = 10.200 ns; Loc. = LC3_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[18\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[18] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 10.500 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\] 20 COMB LC4_C17 2 " "Info: 20: + IC(0.000 ns) + CELL(0.300 ns) = 10.500 ns; Loc. = LC4_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[19\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[19] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 10.800 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\] 21 COMB LC5_C17 2 " "Info: 21: + IC(0.000 ns) + CELL(0.300 ns) = 10.800 ns; Loc. = LC5_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[20\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[20] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 11.100 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\] 22 COMB LC6_C17 2 " "Info: 22: + IC(0.000 ns) + CELL(0.300 ns) = 11.100 ns; Loc. = LC6_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[21\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[21] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 11.400 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\] 23 COMB LC7_C17 2 " "Info: 23: + IC(0.000 ns) + CELL(0.300 ns) = 11.400 ns; Loc. = LC7_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[22\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[22] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 11.700 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\] 24 COMB LC8_C17 2 " "Info: 24: + IC(0.000 ns) + CELL(0.300 ns) = 11.700 ns; Loc. = LC8_C17; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[23\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[23] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.800 ns) + CELL(0.300 ns) 12.800 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\] 25 COMB LC1_C19 2 " "Info: 25: + IC(0.800 ns) + CELL(0.300 ns) = 12.800 ns; Loc. = LC1_C19; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[24\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "1.100 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[23] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[24] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 13.100 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\] 26 COMB LC2_C19 2 " "Info: 26: + IC(0.000 ns) + CELL(0.300 ns) = 13.100 ns; Loc. = LC2_C19; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[25\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[24] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[25] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 13.400 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\] 27 COMB LC3_C19 2 " "Info: 27: + IC(0.000 ns) + CELL(0.300 ns) = 13.400 ns; Loc. = LC3_C19; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[26\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[25] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[26] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 13.700 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\] 28 COMB LC4_C19 2 " "Info: 28: + IC(0.000 ns) + CELL(0.300 ns) = 13.700 ns; Loc. = LC4_C19; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[27\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[26] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[27] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 14.000 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\] 29 COMB LC5_C19 2 " "Info: 29: + IC(0.000 ns) + CELL(0.300 ns) = 14.000 ns; Loc. = LC5_C19; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[28\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[27] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[28] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 14.300 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\] 30 COMB LC6_C19 2 " "Info: 30: + IC(0.000 ns) + CELL(0.300 ns) = 14.300 ns; Loc. = LC6_C19; Fanout = 2; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[29\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[28] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[29] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 14.600 ns lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\] 31 COMB LC7_C19 1 " "Info: 31: + IC(0.000 ns) + CELL(0.300 ns) = 14.600 ns; Loc. = LC7_C19; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|a_csnbuffer:result_node\|cout\[30\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "0.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[29] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[30] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 15.900 ns lpm_add_sub:add_rtl_4\|addcore:adder\|unreg_res_node\[31\] 32 COMB LC8_C19 1 " "Info: 32: + IC(0.000 ns) + CELL(1.300 ns) = 15.900 ns; Loc. = LC8_C19; Fanout = 1; COMB Node = 'lpm_add_sub:add_rtl_4\|addcore:adder\|unreg_res_node\[31\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "1.300 ns" { lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[30] lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[31] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/addcore.tdf" 95 16 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(1.200 ns) 19.300 ns num_clk2\[31\] 33 REG LC3_C20 2 " "Info: 33: + IC(2.200 ns) + CELL(1.200 ns) = 19.300 ns; Loc. = LC3_C20; Fanout = 2; REG Node = 'num_clk2\[31\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "3.400 ns" { lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[31] num_clk2[31] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.400 ns 64.25 % " "Info: Total cell delay = 12.400 ns ( 64.25 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns 35.75 % " "Info: Total interconnect delay = 6.900 ns ( 35.75 % )" { } { } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "19.300 ns" { num_clk2[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[23] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[24] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[25] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[26] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[27] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[28] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[29] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[30] lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[31] num_clk2[31] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "19.300 ns" { num_clk2[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[23] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[24] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[25] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[26] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[27] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[28] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[29] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[30] lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[31] num_clk2[31] } { 0.000ns 2.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clock\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 66 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 66; CLK Node = 'clock'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { clock } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns num_clk2\[31\] 2 REG LC3_C20 2 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_C20; Fanout = 2; REG Node = 'num_clk2\[31\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "2.500 ns" { clock num_clk2[31] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "5.300 ns" { clock num_clk2[31] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out num_clk2[31] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clock\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 66 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 66; CLK Node = 'clock'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { clock } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns num_clk2\[1\] 2 REG LC1_C14 3 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC1_C14; Fanout = 3; REG Node = 'num_clk2\[1\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "2.500 ns" { clock num_clk2[1] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns 52.83 % " "Info: Total cell delay = 2.800 ns ( 52.83 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns 47.17 % " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" { } { } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "5.300 ns" { clock num_clk2[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out num_clk2[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "5.300 ns" { clock num_clk2[31] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out num_clk2[31] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "5.300 ns" { clock num_clk2[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out num_clk2[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 31 -1 0 } } } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "19.300 ns" { num_clk2[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[23] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[24] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[25] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[26] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[27] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[28] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[29] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[30] lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[31] num_clk2[31] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "19.300 ns" { num_clk2[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[1] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[2] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[3] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[4] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[5] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[6] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[7] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[8] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[9] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[10] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[11] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[12] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[13] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[14] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[15] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[16] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[17] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[18] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[19] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[20] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[21] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[22] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[23] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[24] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[25] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[26] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[27] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[28] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[29] lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[30] lpm_add_sub:add_rtl_4|addcore:adder|unreg_res_node[31] num_clk2[31] } { 0.000ns 2.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.800ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.200ns } { 0.000ns 1.200ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.300ns 1.200ns } } } { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "5.300 ns" { clock num_clk2[31] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out num_clk2[31] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "5.300 ns" { clock num_clk2[1] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "5.300 ns" { clock clock~out num_clk2[1] } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "r_temp\[6\] rxd clock 15.100 ns register " "Info: tsu for register \"r_temp\[6\]\" (data pin = \"rxd\", clock pin = \"clock\") is 15.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.600 ns + Longest pin register " "Info: + Longest pin to register delay is 23.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns rxd 1 PIN PIN_53 4 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_53; Fanout = 4; PIN Node = 'rxd'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { rxd } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.400 ns) + CELL(1.800 ns) 9.700 ns always3~0 2 COMB LC1_A7 11 " "Info: 2: + IC(4.400 ns) + CELL(1.800 ns) = 9.700 ns; Loc. = LC1_A7; Fanout = 11; COMB Node = 'always3~0'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "6.200 ns" { rxd always3~0 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(2.300 ns) 14.400 ns n\[3\]~85 3 COMB LC3_A6 13 " "Info: 3: + IC(2.400 ns) + CELL(2.300 ns) = 14.400 ns; Loc. = LC3_A6; Fanout = 13; COMB Node = 'n\[3\]~85'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "4.700 ns" { always3~0 n[3]~85 } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 17.300 ns r_temp\[6\]~195 4 COMB LC1_A6 3 " "Info: 4: + IC(0.600 ns) + CELL(2.300 ns) = 17.300 ns; Loc. = LC1_A6; Fanout = 3; COMB Node = 'r_temp\[6\]~195'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "2.900 ns" { n[3]~85 r_temp[6]~195 } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 21.800 ns r_temp\[6\]~196 5 COMB LC6_A9 1 " "Info: 5: + IC(2.200 ns) + CELL(2.300 ns) = 21.800 ns; Loc. = LC6_A9; Fanout = 1; COMB Node = 'r_temp\[6\]~196'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "4.500 ns" { r_temp[6]~195 r_temp[6]~196 } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.200 ns) 23.600 ns r_temp\[6\] 6 REG LC3_A9 10 " "Info: 6: + IC(0.600 ns) + CELL(1.200 ns) = 23.600 ns; Loc. = LC3_A9; Fanout = 10; REG Node = 'r_temp\[6\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "1.800 ns" { r_temp[6]~196 r_temp[6] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "13.400 ns 56.78 % " "Info: Total cell delay = 13.400 ns ( 56.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.200 ns 43.22 % " "Info: Total interconnect delay = 10.200 ns ( 43.22 % )" { } { } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "23.600 ns" { rxd always3~0 n[3]~85 r_temp[6]~195 r_temp[6]~196 r_temp[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "23.600 ns" { rxd rxd~out always3~0 n[3]~85 r_temp[6]~195 r_temp[6]~196 r_temp[6] } { 0.000ns 0.000ns 4.400ns 2.400ns 0.600ns 2.200ns 0.600ns } { 0.000ns 3.500ns 1.800ns 2.300ns 2.300ns 2.300ns 1.200ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" { } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 11.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clock\" to destination register is 11.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clock 1 CLK PIN_43 66 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 66; CLK Node = 'clock'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "" { clock } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 3 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(1.100 ns) 6.400 ns clk 2 REG LC1_B14 26 " "Info: 2: + IC(2.500 ns) + CELL(1.100 ns) = 6.400 ns; Loc. = LC1_B14; Fanout = 26; REG Node = 'clk'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "3.600 ns" { clock clk } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 22 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.600 ns) + CELL(0.000 ns) 11.000 ns r_temp\[6\] 3 REG LC3_A9 10 " "Info: 3: + IC(4.600 ns) + CELL(0.000 ns) = 11.000 ns; Loc. = LC3_A9; Fanout = 10; REG Node = 'r_temp\[6\]'" { } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "4.600 ns" { clk r_temp[6] } "NODE_NAME" } "" } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.900 ns 35.45 % " "Info: Total cell delay = 3.900 ns ( 35.45 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.100 ns 64.55 % " "Info: Total interconnect delay = 7.100 ns ( 64.55 % )" { } { } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "11.000 ns" { clock clk r_temp[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out clk r_temp[6] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0} } { { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "23.600 ns" { rxd always3~0 n[3]~85 r_temp[6]~195 r_temp[6]~196 r_temp[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "23.600 ns" { rxd rxd~out always3~0 n[3]~85 r_temp[6]~195 r_temp[6]~196 r_temp[6] } { 0.000ns 0.000ns 4.400ns 2.400ns 0.600ns 2.200ns 0.600ns } { 0.000ns 3.500ns 1.800ns 2.300ns 2.300ns 2.300ns 1.200ns } } } { "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" "" { Report "E:/Projects/FPGA/Uart_TR/db/Uart_TR_cmp.qrpt" Compiler "Uart_TR" "UNKNOWN" "V1" "E:/Projects/FPGA/Uart_TR/db/Uart_TR.quartus_db" { Floorplan "E:/Projects/FPGA/Uart_TR/" "" "11.000 ns" { clock clk r_temp[6] } "NODE_NAME" } "" } } { "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus42/bin/Technology_Viewer.qrui" "11.000 ns" { clock clock~out clk r_temp[6] } { 0.000ns 0.000ns 2.500ns 4.600ns } { 0.000ns 2.800ns 1.100ns 0.000ns } } } } 0}
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