uart_tr.map.qmsg

Verilog编写的简单异步串口 完全原创

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.2 Build 157 12/07/2004 SJ Full Version " "Info: Version 4.2 Build 157 12/07/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jul 13 09:44:10 2006 " "Info: Processing started: Thu Jul 13 09:44:10 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off Uart_TR -c Uart_TR " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Uart_TR -c Uart_TR" {  } {  } 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "r_buff Uart_TR.v(13) " "Warning: Verilog HDL warning at Uart_TR.v(13): using specified range for net, port, or variable \"r_buff\" that was previously declared without a range specification" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 13 0 0 } }  } 0}
{ "Info" "ISGN_SEARCH_FILE" "Uart_TR.v 1 1 " "Info: Using design file Uart_TR.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 Uart_TR " "Info: Found entity 1: Uart_TR" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "6 5 Uart_TR.v(69) " "Warning: Verilog HDL assignment warning at Uart_TR.v(69): truncated value with size 6 to match size of target (5)" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 69 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 Uart_TR.v(96) " "Warning: Verilog HDL assignment warning at Uart_TR.v(96): truncated value with size 5 to match size of target (4)" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 96 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 Uart_TR.v(128) " "Warning: Verilog HDL assignment warning at Uart_TR.v(128): truncated value with size 5 to match size of target (4)" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 128 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "5 4 Uart_TR.v(141) " "Warning: Verilog HDL assignment warning at Uart_TR.v(141): truncated value with size 5 to match size of target (4)" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 141 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Info: Inferred 2 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "n\[0\]~40 4 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: \"n\[0\]~40\"" {  } { { "Uart_TR.v" "n\[0\]~40" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 171 -1 0 } }  } 0} { "Info" "IOPT_LPM_COUNTER_INFERRED" "s\[0\]~10 5 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: \"s\[0\]~10\"" {  } { { "Uart_TR.v" "s\[0\]~10" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 41 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus42/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_counter_f10ke " "Info: Found entity 1: alt_counter_f10ke" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf" 256 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf" 106 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus42/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/altera/quartus42/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/program files/altera/quartus42/libraries/megafunctions/altshift.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 41 -1 0 } } { "Uart_TR.v" "" { Text "E:/Projects/FPGA/Uart_TR/Uart_TR.v" 41 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "238 " "Info: Implemented 238 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "226 " "Info: Implemented 226 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 5 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 13 09:44:15 2006 " "Info: Processing ended: Thu Jul 13 09:44:15 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}