uart_tr.map.eqn

Verilog编写的简单异步串口 完全原创

--F6_cs_buffer[16] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[16]
--operation mode is arithmetic

F6_cs_buffer[16] = num_clk[16] $ (F6_cout[15]);

--F6_cout[16] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[16]
--operation mode is arithmetic

F6_cout[16] = CARRY(num_clk[16] & F6_cout[15]);


--F6_cs_buffer[23] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[23]
--operation mode is arithmetic

F6_cs_buffer[23] = num_clk[23] $ (F6_cout[22]);

--F6_cout[23] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[23]
--operation mode is arithmetic

F6_cout[23] = CARRY(num_clk[23] & F6_cout[22]);


--F6_cs_buffer[22] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[22]
--operation mode is arithmetic

F6_cs_buffer[22] = num_clk[22] $ (F6_cout[21]);

--F6_cout[22] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[22]
--operation mode is arithmetic

F6_cout[22] = CARRY(num_clk[22] & F6_cout[21]);


--F6_cs_buffer[21] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[21]
--operation mode is arithmetic

F6_cs_buffer[21] = num_clk[21] $ (F6_cout[20]);

--F6_cout[21] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[21]
--operation mode is arithmetic

F6_cout[21] = CARRY(num_clk[21] & F6_cout[20]);


--F6_cs_buffer[20] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[20]
--operation mode is arithmetic

F6_cs_buffer[20] = num_clk[20] $ (F6_cout[19]);

--F6_cout[20] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[20]
--operation mode is arithmetic

F6_cout[20] = CARRY(num_clk[20] & F6_cout[19]);


--F6_cs_buffer[11] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[11]
--operation mode is arithmetic

F6_cs_buffer[11] = num_clk[11] $ (F6_cout[10]);

--F6_cout[11] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[11]
--operation mode is arithmetic

F6_cout[11] = CARRY(num_clk[11] & F6_cout[10]);


--F6_cs_buffer[10] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[10]
--operation mode is arithmetic

F6_cs_buffer[10] = num_clk[10] $ (F6_cout[9]);

--F6_cout[10] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[10]
--operation mode is arithmetic

F6_cout[10] = CARRY(num_clk[10] & F6_cout[9]);


--F6_cs_buffer[9] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[9]
--operation mode is arithmetic

F6_cs_buffer[9] = num_clk[9] $ (F6_cout[8]);

--F6_cout[9] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[9]
--operation mode is arithmetic

F6_cout[9] = CARRY(num_clk[9] & F6_cout[8]);


--F6_cs_buffer[8] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[8]
--operation mode is arithmetic

F6_cs_buffer[8] = num_clk[8] $ (F6_cout[7]);

--F6_cout[8] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[8]
--operation mode is arithmetic

F6_cout[8] = CARRY(num_clk[8] & F6_cout[7]);


--F6_cs_buffer[15] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[15]
--operation mode is arithmetic

F6_cs_buffer[15] = num_clk[15] $ (F6_cout[14]);

--F6_cout[15] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[15]
--operation mode is arithmetic

F6_cout[15] = CARRY(num_clk[15] & F6_cout[14]);


--F6_cs_buffer[14] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[14]
--operation mode is arithmetic

F6_cs_buffer[14] = num_clk[14] $ (F6_cout[13]);

--F6_cout[14] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[14]
--operation mode is arithmetic

F6_cout[14] = CARRY(num_clk[14] & F6_cout[13]);


--F6_cs_buffer[13] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[13]
--operation mode is arithmetic

F6_cs_buffer[13] = num_clk[13] $ (F6_cout[12]);

--F6_cout[13] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[13]
--operation mode is arithmetic

F6_cout[13] = CARRY(num_clk[13] & F6_cout[12]);


--F6_cs_buffer[12] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[12]
--operation mode is arithmetic

F6_cs_buffer[12] = num_clk[12] $ (F6_cout[11]);

--F6_cout[12] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[12]
--operation mode is arithmetic

F6_cout[12] = CARRY(num_clk[12] & F6_cout[11]);


--F6_cs_buffer[3] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]
--operation mode is arithmetic

F6_cs_buffer[3] = num_clk[3] $ (F6_cout[2]);

--F6_cout[3] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[3]
--operation mode is arithmetic

F6_cout[3] = CARRY(num_clk[3] & F6_cout[2]);


--F6_cs_buffer[2] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]
--operation mode is arithmetic

F6_cs_buffer[2] = num_clk[2] $ (F6_cout[1]);

--F6_cout[2] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[2]
--operation mode is arithmetic

F6_cout[2] = CARRY(num_clk[2] & F6_cout[1]);


--F6_cs_buffer[1] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]
--operation mode is arithmetic

F6_cs_buffer[1] = num_clk[1] $ (F6_cout[0]);

--F6_cout[1] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[1]
--operation mode is arithmetic

F6_cout[1] = CARRY(num_clk[1] & F6_cout[0]);


--F6_cs_buffer[6] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[6]
--operation mode is arithmetic

F6_cs_buffer[6] = num_clk[6] $ (F6_cout[5]);

--F6_cout[6] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[6]
--operation mode is arithmetic

F6_cout[6] = CARRY(num_clk[6] & F6_cout[5]);


--F6_cs_buffer[7] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[7]
--operation mode is arithmetic

F6_cs_buffer[7] = num_clk[7] $ (F6_cout[6]);

--F6_cout[7] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[7]
--operation mode is arithmetic

F6_cout[7] = CARRY(num_clk[7] & F6_cout[6]);


--F6_cs_buffer[5] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]
--operation mode is arithmetic

F6_cs_buffer[5] = num_clk[5] $ (F6_cout[4]);

--F6_cout[5] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[5]
--operation mode is arithmetic

F6_cout[5] = CARRY(num_clk[5] & F6_cout[4]);


--F6_cs_buffer[4] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]
--operation mode is arithmetic

F6_cs_buffer[4] = num_clk[4] $ (F6_cout[3]);

--F6_cout[4] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[4]
--operation mode is arithmetic

F6_cout[4] = CARRY(num_clk[4] & F6_cout[3]);


--num_clk2[27] is num_clk2[27]
--operation mode is normal

num_clk2[27]_lut_out = F9_cs_buffer[27];
num_clk2[27] = DFFEA(num_clk2[27]_lut_out, clock, , , , , );


--num_clk2[26] is num_clk2[26]
--operation mode is normal

num_clk2[26]_lut_out = F9_cs_buffer[26];
num_clk2[26] = DFFEA(num_clk2[26]_lut_out, clock, , , , , );


--num_clk2[25] is num_clk2[25]
--operation mode is normal

num_clk2[25]_lut_out = F9_cs_buffer[25];
num_clk2[25] = DFFEA(num_clk2[25]_lut_out, clock, , , , , );


--num_clk2[24] is num_clk2[24]
--operation mode is normal

num_clk2[24]_lut_out = F9_cs_buffer[24];
num_clk2[24] = DFFEA(num_clk2[24]_lut_out, clock, , , , , );


--A1L041 is reduce_nor~666
--operation mode is normal

A1L041 = !num_clk2[27] & !num_clk2[26] & !num_clk2[25] & !num_clk2[24];


--num_clk2[31] is num_clk2[31]
--operation mode is normal

num_clk2[31]_lut_out = D3_unreg_res_node[31];
num_clk2[31] = DFFEA(num_clk2[31]_lut_out, clock, , , , , );


--num_clk2[30] is num_clk2[30]
--operation mode is normal

num_clk2[30]_lut_out = F9_cs_buffer[30];
num_clk2[30] = DFFEA(num_clk2[30]_lut_out, clock, , , , , );


--num_clk2[29] is num_clk2[29]
--operation mode is normal

num_clk2[29]_lut_out = F9_cs_buffer[29];
num_clk2[29] = DFFEA(num_clk2[29]_lut_out, clock, , , , , );


--num_clk2[28] is num_clk2[28]
--operation mode is normal

num_clk2[28]_lut_out = F9_cs_buffer[28];
num_clk2[28] = DFFEA(num_clk2[28]_lut_out, clock, , , , , );


--A1L841 is reduce_nor~678
--operation mode is normal

A1L841 = (!num_clk2[31] & !num_clk2[30] & !num_clk2[29] & !num_clk2[28]) & CASCADE(A1L041);


--num_clk2[19] is num_clk2[19]
--operation mode is normal

num_clk2[19]_lut_out = F9_cs_buffer[19];
num_clk2[19] = DFFEA(num_clk2[19]_lut_out, clock, , , , , );


--num_clk2[18] is num_clk2[18]
--operation mode is normal

num_clk2[18]_lut_out = F9_cs_buffer[18];
num_clk2[18] = DFFEA(num_clk2[18]_lut_out, clock, , , , , );


--num_clk2[17] is num_clk2[17]
--operation mode is normal

num_clk2[17]_lut_out = F9_cs_buffer[17];
num_clk2[17] = DFFEA(num_clk2[17]_lut_out, clock, , , , , );


--num_clk2[16] is num_clk2[16]
--operation mode is normal

num_clk2[16]_lut_out = F9_cs_buffer[16];
num_clk2[16] = DFFEA(num_clk2[16]_lut_out, clock, , , , , );


--A1L141 is reduce_nor~668
--operation mode is normal

A1L141 = !num_clk2[19] & !num_clk2[18] & !num_clk2[17] & !num_clk2[16];


--num_clk2[23] is num_clk2[23]
--operation mode is normal

num_clk2[23]_lut_out = F9_cs_buffer[23];
num_clk2[23] = DFFEA(num_clk2[23]_lut_out, clock, , , , , );


--num_clk2[22] is num_clk2[22]
--operation mode is normal

num_clk2[22]_lut_out = F9_cs_buffer[22];
num_clk2[22] = DFFEA(num_clk2[22]_lut_out, clock, , , , , );


--num_clk2[21] is num_clk2[21]
--operation mode is normal

num_clk2[21]_lut_out = F9_cs_buffer[21];
num_clk2[21] = DFFEA(num_clk2[21]_lut_out, clock, , , , , );


--num_clk2[20] is num_clk2[20]
--operation mode is normal

num_clk2[20]_lut_out = F9_cs_buffer[20];
num_clk2[20] = DFFEA(num_clk2[20]_lut_out, clock, , , , , );


--A1L941 is reduce_nor~679
--operation mode is normal

A1L941 = (!num_clk2[23] & !num_clk2[22] & !num_clk2[21] & !num_clk2[20]) & CASCADE(A1L141);


--num_clk2[10] is num_clk2[10]
--operation mode is normal

num_clk2[10]_lut_out = A1L531 & F9_cs_buffer[10];
num_clk2[10] = DFFEA(num_clk2[10]_lut_out, clock, , , , , );


--num_clk2[11] is num_clk2[11]
--operation mode is normal

num_clk2[11]_lut_out = F9_cs_buffer[11];
num_clk2[11] = DFFEA(num_clk2[11]_lut_out, clock, , , , , );


--num_clk2[9] is num_clk2[9]
--operation mode is normal

num_clk2[9]_lut_out = F9_cs_buffer[9];
num_clk2[9] = DFFEA(num_clk2[9]_lut_out, clock, , , , , );


--num_clk2[8] is num_clk2[8]
--operation mode is normal

num_clk2[8]_lut_out = F9_cs_buffer[8];
num_clk2[8] = DFFEA(num_clk2[8]_lut_out, clock, , , , , );


--A1L241 is reduce_nor~670
--operation mode is normal

A1L241 = num_clk2[10] & !num_clk2[11] & !num_clk2[9] & !num_clk2[8];


--num_clk2[15] is num_clk2[15]
--operation mode is normal

num_clk2[15]_lut_out = F9_cs_buffer[15];
num_clk2[15] = DFFEA(num_clk2[15]_lut_out, clock, , , , , );


--num_clk2[14] is num_clk2[14]
--operation mode is normal

num_clk2[14]_lut_out = F9_cs_buffer[14];
num_clk2[14] = DFFEA(num_clk2[14]_lut_out, clock, , , , , );


--num_clk2[13] is num_clk2[13]
--operation mode is normal

num_clk2[13]_lut_out = F9_cs_buffer[13];
num_clk2[13] = DFFEA(num_clk2[13]_lut_out, clock, , , , , );


--num_clk2[12] is num_clk2[12]
--operation mode is normal

num_clk2[12]_lut_out = F9_cs_buffer[12];
num_clk2[12] = DFFEA(num_clk2[12]_lut_out, clock, , , , , );


--A1L051 is reduce_nor~680
--operation mode is normal

A1L051 = (!num_clk2[15] & !num_clk2[14] & !num_clk2[13] & !num_clk2[12]) & CASCADE(A1L241);


--num_clk2[1] is num_clk2[1]
--operation mode is normal

num_clk2[1]_lut_out = A1L531 & F9_cs_buffer[1];
num_clk2[1] = DFFEA(num_clk2[1]_lut_out, clock, , , , , );


--num_clk2[3] is num_clk2[3]
--operation mode is normal

num_clk2[3]_lut_out = F9_cs_buffer[3];
num_clk2[3] = DFFEA(num_clk2[3]_lut_out, clock, , , , , );


--num_clk2[2] is num_clk2[2]
--operation mode is normal

num_clk2[2]_lut_out = F9_cs_buffer[2];
num_clk2[2] = DFFEA(num_clk2[2]_lut_out, clock, , , , , );


--num_clk2[0] is num_clk2[0]
--operation mode is arithmetic

num_clk2[0]_lut_out = !num_clk2[0] & A1L531;
num_clk2[0] = DFFEA(num_clk2[0]_lut_out, clock, , , , , );

--F9_cout[0] is lpm_add_sub:add_rtl_4|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

F9_cout[0] = CARRY(num_clk2[0]);


--A1L341 is reduce_nor~672
--operation mode is normal

A1L341 = num_clk2[1] & !num_clk2[3] & !num_clk2[2] & !num_clk2[0];


--num_clk2[7] is num_clk2[7]
--operation mode is normal

num_clk2[7]_lut_out = A1L531 & F9_cs_buffer[7];
num_clk2[7] = DFFEA(num_clk2[7]_lut_out, clock, , , , , );


--num_clk2[6] is num_clk2[6]