uart_tr.map.eqn

Verilog编写的简单异步串口 完全原创

G2_q[0] = DFFEA(G2_q[0]_lut_out, clk2, !btn, , , , );

--G2L3 is lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT
--operation mode is clrb_cntr

G2L3 = CARRY(G2_q[0]);


--G2_q[1] is lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter|q[1]
--operation mode is clrb_cntr

G2_q[1]_lut_out = (G2_q[1] $ (G2L11 & G2L3)) & G2L21;
G2_q[1] = DFFEA(G2_q[1]_lut_out, clk2, !btn, , , , );

--G2L5 is lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT
--operation mode is clrb_cntr

G2L5 = CARRY(G2_q[1] & G2L3);


--A1L3 is Mux~10
--operation mode is normal

A1L3 = G2_q[0] & G2_q[1] # !G2_q[0] & G2_q[1] & A1L121Q # !G2_q[1] & A1L511Q;


--A1L4 is Mux~11
--operation mode is normal

A1L4 = G2_q[0] & A1L3 & A1L421Q # !A1L3 & A1L811Q # !G2_q[0] & A1L3;


--A1L061 is txd~61
--operation mode is normal

A1L061 = A1L951 # fs & G2_q[2] & A1L4;


--A1L1 is Mux~8
--operation mode is normal

A1L1 = G2_q[1] & G2_q[0] # !G2_q[1] & G2_q[0] & A1L601Q # !G2_q[0] & A1L301Q;


--A1L2 is Mux~9
--operation mode is normal

A1L2 = G2_q[1] & A1L1 & A1L211Q # !A1L1 & A1L901Q # !G2_q[1] & A1L1;


--A1L161 is txd~62
--operation mode is normal

A1L161 = A1L061 # fs & A1L2 & !G2_q[2];


--A1L531 is reduce_nor~1
--operation mode is normal

A1L531 = !A1L151 # !A1L051 # !A1L941 # !A1L841;


--G2L81 is lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter|q[3]~26
--operation mode is normal

G2L81 = !G2_q[4] & !G2_q[3];


--G2L21 is lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~1
--operation mode is normal

G2L21 = !G2_q[4] & !G2_q[3] # !fs;


--num_clk[27] is num_clk[27]
--operation mode is normal

num_clk[27]_lut_out = F6_cs_buffer[27];
num_clk[27] = DFFEA(num_clk[27]_lut_out, clock, , , , , );


--num_clk[26] is num_clk[26]
--operation mode is normal

num_clk[26]_lut_out = F6_cs_buffer[26];
num_clk[26] = DFFEA(num_clk[26]_lut_out, clock, , , , , );


--num_clk[25] is num_clk[25]
--operation mode is normal

num_clk[25]_lut_out = F6_cs_buffer[25];
num_clk[25] = DFFEA(num_clk[25]_lut_out, clock, , , , , );


--num_clk[24] is num_clk[24]
--operation mode is normal

num_clk[24]_lut_out = F6_cs_buffer[24];
num_clk[24] = DFFEA(num_clk[24]_lut_out, clock, , , , , );


--A1L631 is reduce_nor~650
--operation mode is normal

A1L631 = !num_clk[27] & !num_clk[26] & !num_clk[25] & !num_clk[24];


--num_clk[31] is num_clk[31]
--operation mode is normal

num_clk[31]_lut_out = D2_unreg_res_node[31];
num_clk[31] = DFFEA(num_clk[31]_lut_out, clock, , , , , );


--num_clk[30] is num_clk[30]
--operation mode is normal

num_clk[30]_lut_out = F6_cs_buffer[30];
num_clk[30] = DFFEA(num_clk[30]_lut_out, clock, , , , , );


--num_clk[29] is num_clk[29]
--operation mode is normal

num_clk[29]_lut_out = F6_cs_buffer[29];
num_clk[29] = DFFEA(num_clk[29]_lut_out, clock, , , , , );


--num_clk[28] is num_clk[28]
--operation mode is normal

num_clk[28]_lut_out = F6_cs_buffer[28];
num_clk[28] = DFFEA(num_clk[28]_lut_out, clock, , , , , );


--A1L441 is reduce_nor~674
--operation mode is normal

A1L441 = (!num_clk[31] & !num_clk[30] & !num_clk[29] & !num_clk[28]) & CASCADE(A1L631);


--num_clk[19] is num_clk[19]
--operation mode is normal

num_clk[19]_lut_out = F6_cs_buffer[19];
num_clk[19] = DFFEA(num_clk[19]_lut_out, clock, , , , , );


--num_clk[18] is num_clk[18]
--operation mode is normal

num_clk[18]_lut_out = F6_cs_buffer[18];
num_clk[18] = DFFEA(num_clk[18]_lut_out, clock, , , , , );


--num_clk[17] is num_clk[17]
--operation mode is normal

num_clk[17]_lut_out = F6_cs_buffer[17];
num_clk[17] = DFFEA(num_clk[17]_lut_out, clock, , , , , );


--num_clk[16] is num_clk[16]
--operation mode is normal

num_clk[16]_lut_out = F6_cs_buffer[16];
num_clk[16] = DFFEA(num_clk[16]_lut_out, clock, , , , , );


--A1L731 is reduce_nor~652
--operation mode is normal

A1L731 = !num_clk[19] & !num_clk[18] & !num_clk[17] & !num_clk[16];


--num_clk[23] is num_clk[23]
--operation mode is normal

num_clk[23]_lut_out = F6_cs_buffer[23];
num_clk[23] = DFFEA(num_clk[23]_lut_out, clock, , , , , );


--num_clk[22] is num_clk[22]
--operation mode is normal

num_clk[22]_lut_out = F6_cs_buffer[22];
num_clk[22] = DFFEA(num_clk[22]_lut_out, clock, , , , , );


--num_clk[21] is num_clk[21]
--operation mode is normal

num_clk[21]_lut_out = F6_cs_buffer[21];
num_clk[21] = DFFEA(num_clk[21]_lut_out, clock, , , , , );


--num_clk[20] is num_clk[20]
--operation mode is normal

num_clk[20]_lut_out = F6_cs_buffer[20];
num_clk[20] = DFFEA(num_clk[20]_lut_out, clock, , , , , );


--A1L541 is reduce_nor~675
--operation mode is normal

A1L541 = (!num_clk[23] & !num_clk[22] & !num_clk[21] & !num_clk[20]) & CASCADE(A1L731);


--num_clk[11] is num_clk[11]
--operation mode is normal

num_clk[11]_lut_out = F6_cs_buffer[11];
num_clk[11] = DFFEA(num_clk[11]_lut_out, clock, , , , , );


--num_clk[10] is num_clk[10]
--operation mode is normal

num_clk[10]_lut_out = F6_cs_buffer[10];
num_clk[10] = DFFEA(num_clk[10]_lut_out, clock, , , , , );


--num_clk[9] is num_clk[9]
--operation mode is normal

num_clk[9]_lut_out = F6_cs_buffer[9];
num_clk[9] = DFFEA(num_clk[9]_lut_out, clock, , , , , );


--num_clk[8] is num_clk[8]
--operation mode is normal

num_clk[8]_lut_out = F6_cs_buffer[8];
num_clk[8] = DFFEA(num_clk[8]_lut_out, clock, , , , , );


--A1L831 is reduce_nor~654
--operation mode is normal

A1L831 = !num_clk[11] & !num_clk[10] & !num_clk[9] & !num_clk[8];


--num_clk[15] is num_clk[15]
--operation mode is normal

num_clk[15]_lut_out = F6_cs_buffer[15];
num_clk[15] = DFFEA(num_clk[15]_lut_out, clock, , , , , );


--num_clk[14] is num_clk[14]
--operation mode is normal

num_clk[14]_lut_out = F6_cs_buffer[14];
num_clk[14] = DFFEA(num_clk[14]_lut_out, clock, , , , , );


--num_clk[13] is num_clk[13]
--operation mode is normal

num_clk[13]_lut_out = F6_cs_buffer[13];
num_clk[13] = DFFEA(num_clk[13]_lut_out, clock, , , , , );


--num_clk[12] is num_clk[12]
--operation mode is normal

num_clk[12]_lut_out = F6_cs_buffer[12];
num_clk[12] = DFFEA(num_clk[12]_lut_out, clock, , , , , );


--A1L641 is reduce_nor~676
--operation mode is normal

A1L641 = (!num_clk[15] & !num_clk[14] & !num_clk[13] & !num_clk[12]) & CASCADE(A1L831);


--num_clk[3] is num_clk[3]
--operation mode is normal

num_clk[3]_lut_out = A1L431 & F6_cs_buffer[3];
num_clk[3] = DFFEA(num_clk[3]_lut_out, clock, , , , , );


--num_clk[2] is num_clk[2]
--operation mode is normal

num_clk[2]_lut_out = A1L431 & F6_cs_buffer[2];
num_clk[2] = DFFEA(num_clk[2]_lut_out, clock, , , , , );


--num_clk[1] is num_clk[1]
--operation mode is normal

num_clk[1]_lut_out = A1L431 & F6_cs_buffer[1];
num_clk[1] = DFFEA(num_clk[1]_lut_out, clock, , , , , );


--num_clk[0] is num_clk[0]
--operation mode is arithmetic

num_clk[0]_lut_out = !num_clk[0] & A1L431;
num_clk[0] = DFFEA(num_clk[0]_lut_out, clock, , , , , );

--F6_cout[0] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

F6_cout[0] = CARRY(num_clk[0]);


--A1L931 is reduce_nor~656
--operation mode is normal

A1L931 = num_clk[3] & num_clk[2] & num_clk[1] & !num_clk[0];


--num_clk[6] is num_clk[6]
--operation mode is normal

num_clk[6]_lut_out = A1L431 & F6_cs_buffer[6];
num_clk[6] = DFFEA(num_clk[6]_lut_out, clock, , , , , );


--num_clk[7] is num_clk[7]
--operation mode is normal

num_clk[7]_lut_out = F6_cs_buffer[7];
num_clk[7] = DFFEA(num_clk[7]_lut_out, clock, , , , , );


--num_clk[5] is num_clk[5]
--operation mode is normal

num_clk[5]_lut_out = F6_cs_buffer[5];
num_clk[5] = DFFEA(num_clk[5]_lut_out, clock, , , , , );


--num_clk[4] is num_clk[4]
--operation mode is normal

num_clk[4]_lut_out = F6_cs_buffer[4];
num_clk[4] = DFFEA(num_clk[4]_lut_out, clock, , , , , );


--A1L741 is reduce_nor~677
--operation mode is normal

A1L741 = (num_clk[6] & !num_clk[7] & !num_clk[5] & !num_clk[4]) & CASCADE(A1L931);


--D1_unreg_res_node[3] is lpm_add_sub:add_rtl_2|addcore:adder|unreg_res_node[3]
--operation mode is normal

D1_unreg_res_node[3] = F3_cout[2] $ i[3];


--G2L11 is lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]~0
--operation mode is normal

G2L11 = fs & !fc;


--F6_cs_buffer[27] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[27]
--operation mode is arithmetic

F6_cs_buffer[27] = num_clk[27] $ (F6_cout[26]);

--F6_cout[27] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[27]
--operation mode is arithmetic

F6_cout[27] = CARRY(num_clk[27] & F6_cout[26]);


--F6_cs_buffer[26] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[26]
--operation mode is arithmetic

F6_cs_buffer[26] = num_clk[26] $ (F6_cout[25]);

--F6_cout[26] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[26]
--operation mode is arithmetic

F6_cout[26] = CARRY(num_clk[26] & F6_cout[25]);


--F6_cs_buffer[25] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[25]
--operation mode is arithmetic

F6_cs_buffer[25] = num_clk[25] $ (F6_cout[24]);

--F6_cout[25] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[25]
--operation mode is arithmetic

F6_cout[25] = CARRY(num_clk[25] & F6_cout[24]);


--F6_cs_buffer[24] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[24]
--operation mode is arithmetic

F6_cs_buffer[24] = num_clk[24] $ (F6_cout[23]);

--F6_cout[24] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[24]
--operation mode is arithmetic

F6_cout[24] = CARRY(num_clk[24] & F6_cout[23]);


--F6_cs_buffer[30] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[30]
--operation mode is arithmetic

F6_cs_buffer[30] = num_clk[30] $ (F6_cout[29]);

--F6_cout[30] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[30]
--operation mode is arithmetic

F6_cout[30] = CARRY(num_clk[30] & F6_cout[29]);


--F6_cs_buffer[29] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[29]
--operation mode is arithmetic

F6_cs_buffer[29] = num_clk[29] $ (F6_cout[28]);

--F6_cout[29] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[29]
--operation mode is arithmetic

F6_cout[29] = CARRY(num_clk[29] & F6_cout[28]);


--F6_cs_buffer[28] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[28]
--operation mode is arithmetic

F6_cs_buffer[28] = num_clk[28] $ (F6_cout[27]);

--F6_cout[28] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[28]
--operation mode is arithmetic

F6_cout[28] = CARRY(num_clk[28] & F6_cout[27]);


--F6_cs_buffer[19] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[19]
--operation mode is arithmetic

F6_cs_buffer[19] = num_clk[19] $ (F6_cout[18]);

--F6_cout[19] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[19]
--operation mode is arithmetic

F6_cout[19] = CARRY(num_clk[19] & F6_cout[18]);


--F6_cs_buffer[18] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[18]
--operation mode is arithmetic

F6_cs_buffer[18] = num_clk[18] $ (F6_cout[17]);

--F6_cout[18] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[18]
--operation mode is arithmetic

F6_cout[18] = CARRY(num_clk[18] & F6_cout[17]);


--F6_cs_buffer[17] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cs_buffer[17]
--operation mode is arithmetic

F6_cs_buffer[17] = num_clk[17] $ (F6_cout[16]);

--F6_cout[17] is lpm_add_sub:add_rtl_3|addcore:adder|a_csnbuffer:result_node|cout[17]
--operation mode is arithmetic

F6_cout[17] = CARRY(num_clk[17] & F6_cout[16]);