uart_tr.v

Verilog编写的简单异步串口 完全原创

module Uart_TR (btn,clock,r_buff,txd,rxd);

input btn,clock,rxd;
output r_buff,txd;

wire btn,clock;
reg clk;
reg clk2;
reg [31:0] num_clk;
reg [31:0] num_clk2;
reg rxd;
reg txd;
reg [7:0] r_buff;
reg rs,rc,dc,t;
reg [3:0] n;
reg [3:0] i;
reg [13:0] r_temp;
reg fs,fc;
reg [4:0] s;

always @ (posedge clock)
	if (num_clk == 78)
		begin
			clk = ~clk;
			num_clk <= 0;
		end
	else
		num_clk <= num_clk+1;
		
always @ (posedge clock)
	if (num_clk2 == 1250)
		begin
			clk2 = ~clk2;
			num_clk2 <= 0;
		end
	else
		num_clk2 <= num_clk2+1;
		
always @ (posedge clk2 or posedge btn)
	begin
		if (btn)
			begin
				//s_buff <= s_buff+1;  //这样会与时钟重叠（出错）
				fs <= 1;
				fc <= 1;
				s <= 0;
			end
		else
			begin
				if (fs)
					begin
						txd <= 0;
						fs <= 0;
					end
				else
					begin
						if (s>7)
							begin
								txd <= 1;
								fc <= 0;
								s <= 0;
								//s_buff <= s_buff+1;
							end
						else
							begin
								if (fc)
									begin
										txd <= r_buff[s];
										s <= s+1;
									end
								else
									txd <= 1'bz;
							end
					end
			end
	end
		
always @ (posedge clk)
	begin
		if ((!rxd)&&(!rc))
			begin
				rs <= 1;
				rc <= 1;
			end
		else
			begin
				if (rs)
					begin
						if (!dc)
							begin
								if (!t)
									begin
										if (n<14)
											begin
												r_temp[n] <= rxd;
												n <= n+1;
											end
										else
											begin
												n <= 0;
												t <= 1;
											end
									end
								else
									begin
										if ((!r_temp[4])&&(!r_temp[5])&&(!r_temp[6]))
											begin
												dc <= 1;
												t <= 0;
											end
										else
											begin
												rc <= 0;
												rs <= 0;
												t <= 0;
											end
									end
							end
						else
							begin
								if (i<8)
									begin
										if (!t)
											begin
												if (n<14)
													begin
														r_temp[n] <= rxd;
														n <= n+1;
													end
												else
													begin
														n <= 0;
														t <= 1;
													end
											end
										else
											begin
												if ((r_temp[4]==r_temp[5])&&(r_temp[5]==r_temp[6]))
													begin
														r_buff[i] <= r_temp[6];
														i <= i+1;
														t <= 0;
													end
												else
													begin
														rc <= 0;
														rs <= 0;
														t <= 0;
													end
											end
									end
								else
									begin
										i <= 0;
										dc <= 0;
										t <= 0;
										rc <= 0;
										rs <= 0;
									end
							end
					end
				else
					begin
						i <= 0;
						dc <= 0;
						t <= 0;
						rc <= 0;
						rs <= 0;
					end
			end
	end
	
endmodule