uart_tr.tan.summary

Verilog编写的简单异步串口 完全原创

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 15.100 ns
From           : rxd
To             : r_temp[4]
From Clock     : 
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.900 ns
From           : always2~0
To             : txd
From Clock     : clock
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.600 ns
From           : rxd
To             : r_temp[4]
From Clock     : 
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 43.67 MHz ( period = 22.900 ns )
From           : num_clk2[1]
To             : num_clk2[31]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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