📄 uart_tr.map.rpt
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; |alt_counter_f10ke:wysi_counter| ; 5 (5) ; 4 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 4 (4) ; 4 (4) ; |Uart_TR|lpm_counter:n_rtl_0|alt_counter_f10ke:wysi_counter ;
; |lpm_counter:s_rtl_1| ; 8 (0) ; 5 ; 0 ; 0 ; 3 (0) ; 0 (0) ; 5 (0) ; 5 (0) ; |Uart_TR|lpm_counter:s_rtl_1 ;
; |alt_counter_f10ke:wysi_counter| ; 8 (8) ; 5 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 5 (5) ; 5 (5) ; |Uart_TR|lpm_counter:s_rtl_1|alt_counter_f10ke:wysi_counter ;
+----------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+----------------------------------------------------------------------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/Projects/FPGA/Uart_TR/Uart_TR.map.eqn.
+----------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------------------------------------------------------------------------+
; Uart_TR.v ; yes ; E:/Projects/FPGA/Uart_TR/Uart_TR.v ;
; lpm_counter.tdf ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal42.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/aglobal42.inc ;
; alt_counter_f10ke.tdf ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf ;
; flex10ke_lcell.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/flex10ke_lcell.inc ;
; lpm_add_sub.tdf ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf ;
; addcore.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/addcore.inc ;
; look_add.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/look_add.inc ;
; bypassff.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/bypassff.inc ;
; altshift.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/altshift.inc ;
; alt_stratix_add_sub.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/alt_mercury_add_sub.inc ;
; addcore.tdf ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/addcore.tdf ;
; a_csnbuffer.inc ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.inc ;
; a_csnbuffer.tdf ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf ;
; altshift.tdf ; yes ; d:/program files/altera/quartus42/libraries/megafunctions/altshift.tdf ;
+----------------------------------+-----------------+-----------------------------------------------------------------------------------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------+
; Resource ; Usage ;
+-----------------------------------+---------+
; Logic cells ; 226 ;
; Total combinational functions ; 159 ;
; Total 4-input functions ; 42 ;
; Total 3-input functions ; 15 ;
; Total 2-input functions ; 30 ;
; Total 1-input functions ; 70 ;
; Total 0-input functions ; 2 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 98 ;
; Total logic cells in carry chains ; 77 ;
; I/O pins ; 12 ;
; Maximum fan-out node ; clock ;
; Maximum fan-out ; 66 ;
; Total fan-out ; 628 ;
; Average fan-out ; 2.64 ;
+-----------------------------------+---------+
+----------------------------------------------------------------+
; WYSIWYG Cells ;
+--------------------------------------------------------+-------+
; Statistic ; Value ;
+--------------------------------------------------------+-------+
; Number of WYSIWYG cells ; 9 ;
; Number of synthesis-generated cells ; 217 ;
; Number of WYSIWYG LUTs ; 9 ;
; Number of synthesis-generated LUTs ; 150 ;
; Number of WYSIWYG registers ; 9 ;
; Number of synthesis-generated registers ; 89 ;
; Number of cells with combinational logic only ; 128 ;
; Number of cells with registers only ; 67 ;
; Number of cells with combinational logic and registers ; 31 ;
+--------------------------------------------------------+-------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 98 ;
; Number of registers using Synchronous Clear ; 9 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 7 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 27 ;
; Number of registers using Output Enable ; 0 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; fs ; 7 ;
; fc ; 2 ;
; Total number of inverted registers = 2 ; ;
+----------------------------------------+---------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.2 Build 157 12/07/2004 SJ Full Version
Info: Processing started: Thu Jul 13 09:44:10 2006
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Uart_TR -c Uart_TR
Warning: Verilog HDL warning at Uart_TR.v(13): using specified range for net, port, or variable "r_buff" that was previously declared without a range specification
Info: Using design file Uart_TR.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: Uart_TR
Warning: Verilog HDL assignment warning at Uart_TR.v(69): truncated value with size 6 to match size of target (5)
Warning: Verilog HDL assignment warning at Uart_TR.v(96): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at Uart_TR.v(128): truncated value with size 5 to match size of target (4)
Warning: Verilog HDL assignment warning at Uart_TR.v(141): truncated value with size 5 to match size of target (4)
Info: Inferred 2 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=4) from the following logic: "n[0]~40"
Info: Inferred lpm_counter megafunction (LPM_WIDTH=5) from the following logic: "s[0]~10"
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file d:/program files/altera/quartus42/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Registers with preset signals will power-up high
Info: Implemented 238 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 9 output pins
Info: Implemented 226 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 5 warnings
Info: Processing ended: Thu Jul 13 09:44:15 2006
Info: Elapsed time: 00:00:05
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