uart_tr.fit.summary

Verilog编写的简单异步串口 完全原创

Flow Status : Successful - Thu Jul 13 09:44:29 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : Uart_TR
Top-level Entity Name : Uart_TR
Family : FLEX10K
Device : EPF10K10LC84-4
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 226 / 576 ( 39 % )
Total pins : 12 / 59 ( 20 % )
Total memory bits : 0 / 6,144 ( 0 % )