📄 timer_send.lst
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(0082) //PORTD=0x3f;
(0083)
(0084) DDRE=0x07; //0000_0011
019A E087 LDI R24,7
019B B982 OUT 0x02,R24
(0085) PORTE=0xfc; //1111_1100
019C EF8C LDI R24,0xFC
019D B983 OUT 0x03,R24
(0086)
(0087) DDRF=0x00; //0000_0000
019E 2422 CLR R2
019F 92200061 STS 0x61,R2
(0088) PORTF=0xff; //1111_1111
01A1 EF8F LDI R24,0xFF
01A2 93800062 STS 0x62,R24
(0089)
(0090) DDRG=0xff; //1111_1111
01A4 93800064 STS 0x64,R24
(0091) PORTG=0x1f; //0001_1111
01A6 E18F LDI R24,0x1F
01A7 93800065 STS 0x65,R24
(0092)
(0093) //enable the interrupt
(0094) //SREG|=0x80; //1000_0000
(0095) //enable the external ram
(0096) MCUCR=(1<<SRE);//使能外部RAM线路
01A9 E880 LDI R24,0x80
01AA BF85 OUT 0x35,R24
(0097)
(0098) EICRA=0x00;
01AB 9220006A STS 0x6A,R2
(0099) EIMSK=0x00;
01AD BE29 OUT 0x39,R2
(0100) //EIMSK=0x01;
(0101)
(0102) return;
01AE 9508 RET
(0103) }
(0104) //-------------------------------------------------------------
(0105) void resethdlc(void)
(0106) {
(0107) PORTD|=0x40; //0100_0000
_resethdlc:
01AF 9A96 SBI 0x12,6
(0108) //PORTD&=0xbf;
(0109) }
01B0 9508 RET
(0110) //--------------------------------------------------------------
(0111) void cshdlc(void)
(0112) {
(0113) PORTD&=0x3f; //0011_1111
_cshdlc:
01B1 B382 IN R24,0x12
01B2 738F ANDI R24,0x3F
01B3 BB82 OUT 0x12,R24
(0114) }
01B4 9508 RET
(0115)
(0116) //-------------------------------------------------------------
(0117) void int_open(void)
(0118) {
(0119) _SEI();
_int_open:
01B5 9478 BSET 7
(0120) asm("nop");
01B6 0000 NOP
(0121) }
01B7 9508 RET
(0122) //--------------------------------------------------------------
(0123) void clk(void)
(0124) {
(0125) PORTD&=0xdf; //1101_1111 片选8254
_clk:
01B8 B382 IN R24,0x12
01B9 7D8F ANDI R24,0xDF
01BA BB82 OUT 0x12,R24
(0126)
(0127) //送入计数方式
(0128) XBYTE[0x3300]=0x36; //地址11_0000_0000 数据0011_0110
01BB E386 LDI R24,0x36
01BC 93803300 STS 0x3300,R24
(0129) XBYTE[0x3000]=0x02; //地址00_0000_0000 数据0000_0010
01BE E082 LDI R24,2
01BF 93803000 STS 0x3000,R24
(0130) XBYTE[0x3000]=0x00; //地址00_0000_0000 数据0000_0000
01C1 2422 CLR R2
01C2 92203000 STS 0x3000,R2
(0131)
(0132) XBYTE[0x3300]=0x76; // 数据0111_0110
01C4 E786 LDI R24,0x76
01C5 93803300 STS 0x3300,R24
(0133) XBYTE[0x3100]=0x02; //地址01_0000_0000 数据0000_0010
01C7 E082 LDI R24,2
01C8 93803100 STS 0x3100,R24
(0134) XBYTE[0x3100]=0x00; //地址01_0000_0000 数据0000_0000
01CA 92203100 STS 0x3100,R2
(0135)
(0136) XBYTE[0x3300]=0xB6; // 数据1011_0110
01CC EB86 LDI R24,0xB6
01CD 93803300 STS 0x3300,R24
(0137) XBYTE[0x3200]=0x02; //地址10_0000_0000 数据0000_0010
01CF E082 LDI R24,2
01D0 93803200 STS 0x3200,R24
(0138) XBYTE[0x3200]=0x00; //地址10_0000_0000 数据0000_0000
01D2 92203200 STS 0x3200,R2
(0139)
(0140) //启动分频计数器
(0141) PORTD|=0x1c; //0001_1100
01D4 B382 IN R24,0x12
01D5 618C ORI R24,0x1C
01D6 BB82 OUT 0x12,R24
(0142)
(0143) //取消片选
(0144) PORTD|=0x20; //0010_0000
01D7 9A95 SBI 0x12,5
(0145) return;
01D8 9508 RET
(0146) }
(0147) //------------------------------------------------------------------
(0148) void automode(void)
(0149) {
(0150) CCR1=0x98; //1001_1000
_automode:
01D9 E988 LDI R24,0x98
01DA 9380202F STS 0x202F,R24
(0151)
(0152) MASB=0xfb; //1111_1011
01DC EF8B LDI R24,0xFB
01DD 93802060 STS 0x2060,R24
(0153) MASK=0x27; //0010_0111
01DF E287 LDI R24,0x27
01E0 93802020 STS 0x2020,R24
(0154) MODE=0x18; //0001_1100 数据传输由HSCX自动管理
01E2 E188 LDI R24,0x18
01E3 93802022 STS 0x2022,R24
(0155) TIMR=0x7f; //监控帧自动重试的次数
01E5 E78F LDI R24,0x7F
01E6 93802023 STS 0x2023,R24
(0156)
(0157) XAD1=0x00; //未知
01E8 2422 CLR R2
01E9 92202023 STS 0x2023,R2
(0158) XAD2=0x03; //未知
01EB E083 LDI R24,3
01EC 93802025 STS 0x2025,R24
(0159) RAH1=0x02; //IMPORMANT!!!
01EE E082 LDI R24,2
01EF 93802026 STS 0x2026,R24
(0160) RAH2=0x00; //IMPORTANT!!!
01F1 92202027 STS 0x2027,R2
(0161) RAL1=0x01; //未知
01F3 E081 LDI R24,1
01F4 93802028 STS 0x2028,R24
(0162) RAL2=0x01; //未知
01F6 93802029 STS 0x2029,R24
(0163) CCR2=0x00; //
01F8 9220202C STS 0x202C,R2
(0164)
(0165)
(0166) XBCH=0x00;
01FA 9220202D STS 0x202D,R2
(0167) while(CEC==1); //等待CMDR可写
01FC 91802021 LDS R24,0x2021
01FE 7084 ANDI R24,4
01FF 9586 LSR R24
0200 9586 LSR R24
0201 3081 CPI R24,1
0202 F3C9 BEQ 0x01FC
(0168) CMDR=0x41; //重启收发器
0203 E481 LDI R24,0x41
0204 93802021 STS 0x2021,R24
(0169) }
0206 9508 RET
_delay_nms:
i_dms --> R20
tm --> R22
0207 940E028A CALL push_gset2
0209 01B8 MOVW R22,R16
(0170) //-----------------------------------------------------------------------
(0171) void delay_nms(unsigned int tm)
(0172) {
(0173) unsigned int i_dms;
(0174) for(i_dms=tm;i_dms>0;i_dms--)
020A 01AB MOVW R20,R22
020B C003 RJMP 0x020F
(0175) delay_1ms();
020C D008 RCALL _delay_1ms
020D 5041 SUBI R20,1
020E 4050 SBCI R21,0
020F 3040 CPI R20,0
0210 0745 CPC R20,R21
0211 F7D1 BNE 0x020C
(0176) }
0212 940E0270 CALL pop_gset2
0214 9508 RET
(0177) //------------------------------------------------------------------
(0178) void delay_1ms(void)
(0179) {
(0180) unsigned int i_dl;
(0181) for(i_dl=1;i_dl<(unsigned int)(4*143-2);i_dl++)
_delay_1ms:
i_dl --> R16
0215 E001 LDI R16,1
0216 E010 LDI R17,0
0217 C002 RJMP 0x021A
0218 5F0F SUBI R16,0xFF
0219 4F1F SBCI R17,0xFF
021A 330A CPI R16,0x3A
021B E0E2 LDI R30,2
021C 071E CPC R17,R30
021D F3D0 BCS 0x0218
(0182) ;
(0183) }
021E 9508 RET
_transmit:
xfw --> R22
it --> R20
021F 940E028A CALL push_gset2
(0184) //------------------------------------------------------------------
(0185) void transmit(void)
(0186) {
(0187) unsigned char it=0;
0221 2744 CLR R20
(0188) unsigned char xfw;
(0189)
(0190) flag_txd=1;
0222 E081 LDI R24,1
0223 93800458 STS _flag_txd,R24
(0191)
(0192) if(count!=0)
0225 90200436 LDS R2,_count
0227 2022 TST R2
0228 F409 BNE 0x022A
0229 C033 RJMP 0x025D
(0193) {
(0194) DeQueue();
022A 940E0110 CALL _DeQueue
(0195)
(0196) while(CEC==1);
022C 91802021 LDS R24,0x2021
022E 7084 ANDI R24,4
022F 9586 LSR R24
0230 9586 LSR R24
0231 3081 CPI R24,1
0232 F3C9 BEQ 0x022C
(0197) do
(0198) {
(0199) xfw=XFW;
0233 91602021 LDS R22,0x2021
0235 7460 ANDI R22,0x40
0236 9566 LSR R22
0237 9566 LSR R22
0238 9566 LSR R22
0239 9566 LSR R22
023A 9566 LSR R22
023B 9566 LSR R22
(0200) }while(xfw!=1);
023C 3061 CPI R22,1
023D F7A9 BNE 0x0233
(0201)
(0202) for(it=0;it<pre_txd[32];it++)
023E 2744 CLR R20
023F C00D RJMP 0x024D
(0203) {
(0204) XFIFO[0x2000+it]=pre_txd[it];
0240 E387 LDI R24,0x37
0241 E094 LDI R25,4
0242 2FE4 MOV R30,R20
0243 27FF CLR R31
0244 0FE8 ADD R30,R24
0245 1FF9 ADC R31,R25
0246 8020 LDD R2,Z+0
0247 2FE4 MOV R30,R20
0248 27FF CLR R31
0249 50E0 SUBI R30,0
024A 4EF0 SBCI R31,0xE0
024B 8220 STD Z+0,R2
024C 9543 INC R20
024D 90200457 LDS R2,0x457
024F 1542 CP R20,R2
0250 F378 BCS 0x0240
(0205) }
(0206)
(0207) while(CEC==1);//等待CMDR可写
0251 91802021 LDS R24,0x2021
0253 7084 ANDI R24,4
0254 9586 LSR R24
0255 9586 LSR R24
0256 3081 CPI R24,1
0257 F3C9 BEQ 0x0251
(0208) CMDR|=0x0a; //写入，引起发送
0258 91802021 LDS R24,0x2021
025A 608A ORI R24,0xA
025B 93802021 STS 0x2021,R24
(0209)
(0210) }
(0211)
(0212) delay_1ms();
025D DFB7 RCALL _delay_1ms
(0213) flag_txd=0;
025E 2422 CLR R2
025F 92200458 STS _flag_txd,R2
(0214)
(0215) }
0261 940E0270 CALL pop_gset2
0263 9508 RET
(0216) //-----------------------------------------------------------------------
(0217) main()
(0218) {
(0219) int im=0;
_main:
im --> R20
0264 2744 CLR R20
0265 2755 CLR R21
(0220)
(0221) chipinit();
0266 DF2B RCALL _chipinit
(0222) clk();
0267 DF50 RCALL _clk
(0223) resethdlc();
0268 DF46 RCALL _resethdlc
(0224) cshdlc();
0269 DF47 RCALL _cshdlc
(0225) automode();
026A DF6E RCALL _automode
(0226) InitQueue();
026B 940E00B7 CALL _InitQueue
(0227) timer0_init();
026D 940E0189 CALL _timer0_init
(0228) int_open();
(0229)
(0230) /*txd[0]=0x02;
(0231) txd[1]=0x93;
(0232) EnQueue(txd,2);
(0233)
(0234) txd[0]=0x02;
(0235) txd[1]=0x00;
(0236) for(im=2;im<17;im++)
(0237) txd[im]=0x99;
(0238) EnQueue(txd,17);
(0239) for(im=0;im<27;im++)
(0240) txd[im]=0xaa;
(0241) EnQueue(txd,27);
(0242)
(0243) delay_nms(1000);
(0244) EnQueue(txd,27);
(0245)
(0246) while(flag_txd);
(0247) transmit();
(0248) while(flag_txd);
(0249) transmit();
(0250) while(flag_txd);
(0251) transmit();*/
(0252)
(0253) }
FILE: <library>
026F CF45 RJMP _int_open
pop_gset2:
0270 E0E2 LDI R30,2
0271 940C0277 JMP pop
push_gset1:
0273 935A ST R21,-Y
0274 934A ST R20,-Y
0275 9508 RET
pop_gset1:
0276 E0E1 LDI R30,1
pop:
0277 9149 LD R20,Y+
0278 9159 LD R21,Y+
0279 FDE0 SBRC R30,0
027A 9508 RET
027B 9169 LD R22,Y+
027C 9179 LD R23,Y+
027D FDE1 SBRC R30,1
027E 9508 RET
027F 90A9 LD R10,Y+
0280 90B9 LD R11,Y+
0281 FDE2 SBRC R30,2
0282 9508 RET
0283 90C9 LD R12,Y+
0284 90D9 LD R13,Y+
0285 FDE3 SBRC R30,3
0286 9508 RET
0287 90E9 LD R14,Y+
0288 90F9 LD R15,Y+
0289 9508 RET
push_gset2:
028A 937A ST R23,-Y
028B 936A ST R22,-Y
028C 940C0273 JMP push_gset1
push_lset:
028E 93FA ST R31,-Y
028F 93EA ST R30,-Y
0290 93BA ST R27,-Y
0291 93AA ST R26,-Y
0292 939A ST R25,-Y
0293 938A ST R24,-Y
0294 933A ST R19,-Y
0295 932A ST R18,-Y
0296 931A ST R17,-Y
0297 930A ST R16,-Y
0298 929A ST R9,-Y
0299 928A ST R8,-Y
029A 927A ST R7,-Y
029B 926A ST R6,-Y
029C 925A ST R5,-Y
029D 924A ST R4,-Y
029E 923A ST R3,-Y
029F 922A ST R2,-Y
02A0 921A ST R1,-Y
02A1 920A ST R0,-Y
02A2 B60F IN R0,0x3F
02A3 920A ST R0,-Y
02A4 9508 RET
pop_lset:
02A5 9009 LD R0,Y+
02A6 BE0F OUT 0x3F,R0
02A7 9009 LD R0,Y+
02A8 9019 LD R1,Y+
02A9 9029 LD R2,Y+
02AA 9039 LD R3,Y+
02AB 9049 LD R4,Y+
02AC 9059 LD R5,Y+
02AD 9069 LD R6,Y+
02AE 9079 LD R7,Y+
02AF 9089 LD R8,Y+
02B0 9099 LD R9,Y+
02B1 9109 LD R16,Y+
02B2 9119 LD R17,Y+
02B3 9129 LD R18,Y+
02B4 9139 LD R19,Y+
02B5 9189 LD R24,Y+
02B6 9199 LD R25,Y+
02B7 91A9 LD R26,Y+
02B8 91B9 LD R27,Y+
02B9 91E9 LD R30,Y+
02BA 91F9 LD R31,Y+
02BB 9508 RET
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