📄 ssx31asa.c
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}
}
if (i >= ulTmt)
{
#ifdef HI_DBG
PRINT ("\r\nnot finish");
#endif
ucRes = ERR;
}
return ucRes;
}
/****************************************************** ENCRYPT DECRYPT ************************************************/
/****************************************************** ENCRYPT DECRYPT ************************************************/
/****************************************************** ENCRYPT DECRYPT ************************************************/
/*
pucRes 4 bytes aligned
*/
ULONG SSX31A_EncryptDecrypt(ULONG ulPhyLink, UCHAR ucFlag, UCHAR* ucKeyIv, UCHAR* pucData, USHORT usDataLen, UCHAR* pucRes)
{
SSX31ADRV_CTRL * pDrvCtrl = (SSX31ADRV_CTRL *)ulPhyLink;
LONG lIntMask;
PEBD_DESC * pCurBD = NULL;
PERD_DESC * pCurRD = NULL;
ULONG ulCnt = 0;
ULONG i;
SSX31A_ICD* pGatherDesc = NULL;
ULONG ulTmt = 0;
UCHAR ucRes = ERR;
SplImp(&lIntMask);
if ( pDrvCtrl->ulCurrDMA1BdReadPtr == ((pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1)) )
{
#ifdef HI_DBG
PRINT("Queue full:BD Read:%d write %d\r\n",
pDrvCtrl->ulCurrDMA1BdReadPtr,
pDrvCtrl->ulCurrDMA1BdWritePtr );
#endif
return ERR;
}
pCurBD = &((PEBD_DESC *)(pDrvCtrl->ulDMA1BDMemBase))[pDrvCtrl->ulCurrDMA1BdWritePtr];
/* icd */
pGatherDesc = (SSX31A_ICD*)Malloc( 2 * sizeof(SSX31A_ICD) );
if (pGatherDesc == NULL)
{
#ifdef HI_DBG
PRINT("SSX31A driver PE send mem alloc fail\r\n");
#endif
return ERR;
}
pCurBD->ulInputContext = (ULONG)virt_to_bus(pGatherDesc);
pCurBD->ulInputNum = 2;
pCurBD->ulInputLength= 32 + usDataLen;
pCurBD->ulGatherEnable = BD_GATHER_ENABLE;
pGatherDesc->ulInputPtr = (ULONG)virt_to_bus(ucKeyIv);
pGatherDesc->ulInputLen = 32;
pGatherDesc->ulInputAttrib = ICD_ATTRIB_LAST_PART;
pGatherDesc->ulOrig = 0;
pGatherDesc ++;
pGatherDesc->ulInputPtr = (ULONG)virt_to_bus(pucData);
pGatherDesc->ulInputLen = usDataLen;
pGatherDesc->ulInputAttrib = ICD_ATTRIB_LAST_PART;
pGatherDesc->ulOrig = 0x04;
/* */
pCurBD->ulOutputContext = virt_to_bus ( (ULONG)pucRes );
pCurBD->ulOutputNum = 0;
pCurBD->ulOutputLength0 = usDataLen;
pCurBD->ulScatterEnable &= ~BD_SCATTER_ENABLE;
pCurBD->ulOpCode = BD_OPCODE_DES_OPERATION;
pCurBD->ulFlag = ucFlag;
#ifdef HI_DBG
{
ULONG* pulTmp = NULL;
ULONG* pulTmp1 = NULL;
int i;
pulTmp = (ULONG*)pCurBD;
printk ("\r\nBD: %08x %08x %08x %08x %08x %08x ", pulTmp[0], pulTmp[1], pulTmp[2], pulTmp[3], pulTmp[4], pulTmp[5]);
pulTmp1 = (ULONG*)((ULONG)bus_to_virt ( pulTmp[1] ));
for (i=0; i<2; i++)
{
printk ("\r\nicd %d: %08x %08x", i, pulTmp1[0], pulTmp1[1]);
pulTmp = (ULONG*)((ULONG)bus_to_virt ( pulTmp1[0] ));
printk ("\r\n buf: %08x %08x %08x %08x %08x %08x %08x %08x", pulTmp[0],pulTmp[1],pulTmp[2],pulTmp[3],pulTmp[4],pulTmp[5],pulTmp[6],pulTmp[7] );
pulTmp1 += 2;
}
}
#endif
pDrvCtrl->ulCurrDMA1BdWritePtr = (pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1);
PciWrite32(SSX31A_BQWP1_RW, pDrvCtrl->ulCurrDMA1BdWritePtr);
pDrvCtrl->ulFreeDMA1BDs --;
SplX(lIntMask);
ulTmt = (DMA1_TMOUT & 0xffff)*100 + 100000;
for (i = 0; i < ulTmt; i ++)
{
UsDelay(10);
PciRead32(SSX31A_BQRP1_RW, &pDrvCtrl->ulCurrDMA1BdReadPtr);
PciRead32(SSX31A_RQWP1_RW, &pDrvCtrl->ulCurrDMA1RdWritePtr);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
continue;
}
else
{
pCurRD = &((PERD_DESC*)(pDrvCtrl->ulDMA1RDMemBase))[pDrvCtrl->ulCurrDMA1RdReadPtr];
#ifdef HI_DBG
{
ULONG* pulTmp = NULL;
pulTmp = (ULONG*)pCurRD;
printk ("\r\nRD %08x %08x %08x %08x %08x %08x",
pulTmp[0],pulTmp[1],pulTmp[2],pulTmp[3],pulTmp[4],pulTmp[5]);
}
#endif
if (pCurRD->ulGatherEnable == BD_GATHER_ENABLE )
{
if (pCurRD->ulInputContext )
{
Free( bus_to_virt(pCurRD->ulInputContext) );
pCurRD->ulInputContext = NULL;
}
}
if (pCurRD->ulScatterEnable == BD_SCATTER_ENABLE )
{
if (pCurRD->ulOutputContext )
{
Free( bus_to_virt(pCurRD->ulOutputContext) );
pCurRD->ulOutputContext = NULL;
}
}
if ((pCurRD->ulStatus & MASK_RD_STATUS_ERRCODE) == RD_STATUS_RDVALID)
{
ucRes = OK;
}
else
{
#ifdef HI_DBG
PRINT("\r\nSSX31A encrypt or decrypt failed. RD status %04x", pCurRD->ulStatus);
ucRes = ERR;
#endif
}
pDrvCtrl->ulCurrDMA1RdReadPtr = (pDrvCtrl->ulCurrDMA1RdReadPtr + 1) & (SSX31A_DMA1_RDQUEUE_LEN - 1);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
PciWrite32(SSX31A_RQRP1_RW, pDrvCtrl->ulCurrDMA1RdReadPtr);
pDrvCtrl->ulFreeDMA1BDs ++;
break;
}
}
}
if (i >= ulTmt)
{
#ifdef HI_DBG
PRINT ("\r\nnot finish");
#endif
ucRes = ERR;
}
return ucRes;
}
/****************************************************** HASH ************************************************/
/****************************************************** HASH ************************************************/
/****************************************************** HASH ************************************************/
/*
pucRes 4 bytes aligned
*/
ULONG SSX31A_Hash(ULONG ulPhyLink, UCHAR ucFlag, UCHAR* ucHmacState, UCHAR* pucData, USHORT usDataLen, UCHAR* pucRes)
{
SSX31ADRV_CTRL * pDrvCtrl = (SSX31ADRV_CTRL *)ulPhyLink;
LONG lIntMask;
PEBD_DESC * pCurBD = NULL;
PERD_DESC * pCurRD = NULL;
ULONG ulCnt = 0;
ULONG i;
SSX31A_ICD* pGatherDesc = NULL;
ULONG ulTmt = 0;
UCHAR ucRes = ERR;
SplImp(&lIntMask);
if ( pDrvCtrl->ulCurrDMA1BdReadPtr == ((pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1)) )
{
#ifdef HI_DBG
PRINT("Queue full:BD Read:%d write %d\r\n",
pDrvCtrl->ulCurrDMA1BdReadPtr,
pDrvCtrl->ulCurrDMA1BdWritePtr );
#endif
return ERR;
}
pCurBD = &((PEBD_DESC *)(pDrvCtrl->ulDMA1BDMemBase))[pDrvCtrl->ulCurrDMA1BdWritePtr];
/* icd */
pGatherDesc = (SSX31A_ICD*)Malloc( 2 * sizeof(SSX31A_ICD) );
if (pGatherDesc == NULL)
{
#ifdef HI_DBG
PRINT("SSX31A driver PE send mem alloc fail\r\n");
#endif
return ERR;
}
pCurBD->ulInputContext = (ULONG)virt_to_bus(pGatherDesc);
pCurBD->ulInputNum = 2;
pCurBD->ulInputLength= 40 + usDataLen;
pCurBD->ulGatherEnable = BD_GATHER_ENABLE;
pGatherDesc->ulInputPtr = (ULONG)virt_to_bus(ucHmacState);
pGatherDesc->ulInputLen = 40;
pGatherDesc->ulInputAttrib = ICD_ATTRIB_LAST_PART;
pGatherDesc->ulOrig = 0;
pGatherDesc ++;
pGatherDesc->ulInputPtr = (ULONG)virt_to_bus(pucData);
pGatherDesc->ulInputLen = usDataLen;
pGatherDesc->ulInputAttrib = ICD_ATTRIB_LAST_PART;
pGatherDesc->ulOrig = 0x04;
/* */
pCurBD->ulOutputContext = virt_to_bus ( (ULONG)pucRes );
pCurBD->ulOutputNum = 0;
pCurBD->ulScatterEnable &= ~BD_SCATTER_ENABLE;
pCurBD->ulOpCode = BD_OPCODE_HASH_OPERATION;
pCurBD->ulFlag = ucFlag;
#ifdef HI_DBG
{
ULONG* pulTmp = NULL;
ULONG* pulTmp1 = NULL;
int i;
pulTmp = (ULONG*)pCurBD;
printk ("\r\nBD: %08x %08x %08x %08x %08x %08x ", pulTmp[0], pulTmp[1], pulTmp[2], pulTmp[3], pulTmp[4], pulTmp[5]);
pulTmp1 = (ULONG*)((ULONG)bus_to_virt ( pulTmp[1] ));
for (i=0; i<2; i++)
{
printk ("\r\nicd %d: %08x %08x", i, pulTmp1[0], pulTmp1[1]);
pulTmp = (ULONG*)((ULONG)bus_to_virt ( pulTmp1[0] ));
printk ("\r\n buf: %08x %08x %08x %08x %08x %08x %08x %08x", pulTmp[0],pulTmp[1],pulTmp[2],pulTmp[3],pulTmp[4],pulTmp[5],pulTmp[6],pulTmp[7] );
pulTmp1 += 2;
}
}
#endif
pDrvCtrl->ulCurrDMA1BdWritePtr = (pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1);
PciWrite32(SSX31A_BQWP1_RW, pDrvCtrl->ulCurrDMA1BdWritePtr);
pDrvCtrl->ulFreeDMA1BDs --;
SplX(lIntMask);
ulTmt = (DMA1_TMOUT & 0xffff)*100 + 100000;
for (i = 0; i < ulTmt; i ++)
{
UsDelay(10);
PciRead32(SSX31A_BQRP1_RW, &pDrvCtrl->ulCurrDMA1BdReadPtr);
PciRead32(SSX31A_RQWP1_RW, &pDrvCtrl->ulCurrDMA1RdWritePtr);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
continue;
}
else
{
pCurRD = &((PERD_DESC*)(pDrvCtrl->ulDMA1RDMemBase))[pDrvCtrl->ulCurrDMA1RdReadPtr];
#ifdef HI_DBG
{
ULONG* pulTmp = NULL;
pulTmp = (ULONG*)pCurRD;
printk ("\r\nRD %08x %08x %08x %08x %08x %08x",
pulTmp[0],pulTmp[1],pulTmp[2],pulTmp[3],pulTmp[4],pulTmp[5]);
}
#endif
if (pCurRD->ulGatherEnable == BD_GATHER_ENABLE )
{
if (pCurRD->ulInputContext )
{
Free( bus_to_virt(pCurRD->ulInputContext) );
pCurRD->ulInputContext = NULL;
}
}
if (pCurRD->ulScatterEnable == BD_SCATTER_ENABLE )
{
if (pCurRD->ulOutputContext )
{
Free( bus_to_virt(pCurRD->ulOutputContext) );
pCurRD->ulOutputContext = NULL;
}
}
if ((pCurRD->ulStatus & MASK_RD_STATUS_ERRCODE) == RD_STATUS_RDVALID)
{
ucRes = OK;
}
else
{
#ifdef HI_DBG
PRINT("\r\nSSX31A hash failed. RD status %04x", pCurRD->ulStatus);
ucRes = ERR;
#endif
}
pDrvCtrl->ulCurrDMA1RdReadPtr = (pDrvCtrl->ulCurrDMA1RdReadPtr + 1) & (SSX31A_DMA1_RDQUEUE_LEN - 1);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
PciWrite32(SSX31A_RQRP1_RW, pDrvCtrl->ulCurrDMA1RdReadPtr);
pDrvCtrl->ulFreeDMA1BDs ++;
break;
}
}
}
if (i >= ulTmt)
{
#ifdef HI_DBG
PRINT ("\r\nnot finish");
#endif
ucRes = ERR;
}
return ucRes;
}⌨️ 快捷键说明
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