📄 ssx31asa.c
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#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include "../def.h"
#include "SSX31ASA.h"
#include "SSX31ADrv.h"
/****************************************************** SA ************************************************/
/****************************************************** SA ************************************************/
/****************************************************** SA ************************************************/
ULONG SSX31A_SendSA(SSX31ADRV_CTRL * pDrvCtrl, UCHAR * p_CardSA, ULONG ulSaID)
{
ULONG ulRes, i;
LONG lIntMask;
PEBD_DESC * pCurSaBD = NULL;
PERD_DESC * pCurSaRD = NULL;
ULONG ulTmt = 0;
ulRes = ERR;
SplImp(&lIntMask);
if (pDrvCtrl->ulCurrDMA1BdReadPtr == ((pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1)))
{
#ifdef HI_DBG
PRINT("BD Queue full:BD Read:%d write %d\r\n",
pDrvCtrl->ulCurrDMA1BdReadPtr,
pDrvCtrl->ulCurrDMA1BdWritePtr);
#endif
return ulRes;
}
pCurSaBD = &((PEBD_DESC *)(pDrvCtrl->ulDMA1BDMemBase))[pDrvCtrl->ulCurrDMA1BdWritePtr];
pCurSaBD->ulOpCode = BD_OPCODE_SA_UPDATE;
pCurSaBD->ulInputContext = virt_to_bus ((ULONG)p_CardSA);
pCurSaBD->ulInputLength = 160;
pCurSaBD->ulOutputContext = ulSaID;
pDrvCtrl->ulCurrDMA1BdWritePtr = (pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1);
PciWrite32(SSX31A_BQWP1_RW, pDrvCtrl->ulCurrDMA1BdWritePtr);
pDrvCtrl->ulFreeDMA1BDs --;
SplX(lIntMask);
ulTmt = (DMA1_TMOUT & 0xffff)*100 + 100000;
for (i = 0; i < ulTmt; i ++)
{
UsDelay(10);
PciRead32(SSX31A_BQRP1_RW, &pDrvCtrl->ulCurrDMA1BdReadPtr);
PciRead32(SSX31A_RQWP1_RW, &pDrvCtrl->ulCurrDMA1RdWritePtr);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
continue;
}
else
{
pCurSaRD = &((PERD_DESC*)(pDrvCtrl->ulDMA1RDMemBase))[pDrvCtrl->ulCurrDMA1RdReadPtr];
if ((pCurSaRD->ulStatus & MASK_RD_STATUS_ERRCODE) == RD_STATUS_RDVALID)
{
ulRes = OK;
}
else
{
#ifdef HI_DBG
PRINT("\r\nSSX31A send SA failed. RD status %04x", pCurSaRD->ulStatus);
#endif
ulRes = ERR;
}
pDrvCtrl->ulCurrDMA1RdReadPtr = (pDrvCtrl->ulCurrDMA1RdReadPtr + 1) & (SSX31A_DMA1_RDQUEUE_LEN - 1);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
PciWrite32(SSX31A_RQRP1_RW, pDrvCtrl->ulCurrDMA1RdReadPtr);
pDrvCtrl->ulFreeDMA1BDs ++;
ulRes = OK;
break;
}
}
}
if (i >= ulTmt)
{
#ifdef HI_DBG
PRINT ("\r\nnot finish");
#endif
ulRes = ERR;
}
return ulRes;
}
ULONG SSX31A_GetSA(SSX31ADRV_CTRL * pDrvCtrl, ULONG ulsaid, UCHAR * pucSA)
{
ULONG ulSaID, ulTemp, ulRes, i;
LONG lIntMask;
PEBD_DESC * pCurSaBD = NULL;
PERD_DESC * pCurSaRD = NULL;
ULONG ulTmt = 0;
ulRes = ERR;
ulSaID = ulsaid;
SplImp(&lIntMask);
if (pDrvCtrl->ulCurrDMA1BdReadPtr == ((pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1)))
{
#ifdef HI_DBG
PRINT("BD Queue full:BD Read:%d write %d\r\n",
pDrvCtrl->ulCurrDMA1BdReadPtr,
pDrvCtrl->ulCurrDMA1BdWritePtr);
#endif
return ulRes;
}
pCurSaBD = &((PEBD_DESC *)(pDrvCtrl->ulDMA1BDMemBase))[pDrvCtrl->ulCurrDMA1BdWritePtr];
pCurSaBD->ulOpCode = BD_OPCODE_SA_READ;
pCurSaBD->ulOutputContext = virt_to_bus ((ULONG)pucSA);
pCurSaBD->ulInputContext = ulSaID;
pCurSaBD->ulInputLength = 1;
pDrvCtrl->ulCurrDMA1BdWritePtr = (pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1);
PciWrite32(SSX31A_BQWP1_RW, pDrvCtrl->ulCurrDMA1BdWritePtr);
pDrvCtrl->ulFreeDMA1BDs --;
SplX(lIntMask);
ulTmt = (DMA1_TMOUT & 0xffff)*100 + 100000;
for (i = 0; i < ulTmt; i ++)
{
UsDelay(10);
PciRead32(SSX31A_BQRP1_RW, &pDrvCtrl->ulCurrDMA1BdReadPtr);
PciRead32(SSX31A_RQWP1_RW, &pDrvCtrl->ulCurrDMA1RdWritePtr);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
continue;
}
else
{
pCurSaRD = &((PERD_DESC*)(pDrvCtrl->ulDMA1RDMemBase))[pDrvCtrl->ulCurrDMA1RdReadPtr];
if ((pCurSaRD->ulStatus & MASK_RD_STATUS_ERRCODE) == RD_STATUS_RDVALID)
{
ulRes = OK;
}
else
{
#ifdef HI_DBG
PRINT("\r\nSSX31A Get SA failed. RD status %04x", pCurSaRD->ulStatus);
#endif
ulRes = ERR;
}
pDrvCtrl->ulCurrDMA1RdReadPtr = (pDrvCtrl->ulCurrDMA1RdReadPtr + 1) & (SSX31A_DMA1_RDQUEUE_LEN - 1);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
PciWrite32(SSX31A_RQRP1_RW, pDrvCtrl->ulCurrDMA1RdReadPtr);
pDrvCtrl->ulFreeDMA1BDs ++;
ulRes = OK;
break;
}
}
}
if (i >= ulTmt)
{
#ifdef HI_DBG
PRINT ("\r\nnot finish");
#endif
ulRes = ERR;
}
return ulRes;
}
ULONG SSX31A_PhyUpdateSA(ULONG ulPhyLink, UCHAR * SA, ULONG ulSaNum)
{
SSX31ADRV_CTRL * pDrvCtrl = (SSX31ADRV_CTRL *)ulPhyLink;
if ( ERR== SSX31A_SendSA(pDrvCtrl, SA, ulSaNum))
{
#ifdef HI_DBG
PRINT("\nSSX31A send SA fail");
#endif
return ERR;
}
#ifdef HI_DBG
{
int i;
ULONG *szSA ;
UCHAR* pucSA;
UCHAR szBuf[160+4] = {0};
pucSA = (UCHAR*)four_bytes_align ((ULONG)szBuf);
if ( ERR == SSX31A_GetSA(pDrvCtrl, ulSaNum, pucSA) )
{
PRINT("\r\nSSX31A get SA fail");
return ERR;
}
if (memcmp (SA, pucSA, 160) == 0 )
{
PRINT("\r\nSSX31 SA Update Success!");
}
else
{
PRINT("\r\nSSX31 SA Update fail!");
PRINT("\r\nSA writed:");
szSA = (ULONG*)SA;
for(i = 0; i < 40; i+=4)
{
PRINT("\r\n0x%08x 0x%08x 0x%08x 0x%08x",
szSA[i], szSA[i+1], szSA[i+2], szSA[i+3] );
}
PRINT("\r\nSA read:");
szSA = (ULONG *)pucSA;
for(i = 0; i < 40; i+=4)
{
PRINT("\r\n0x%08x 0x%08x 0x%08x 0x%08x",
szSA[i], szSA[i+1], szSA[i+2], szSA[i+3] );
}
}
}
#endif
return OK;
}
/****************************************************** RNG ************************************************/
/****************************************************** RNG ************************************************/
/****************************************************** RNG ************************************************/
/*
pucData 4 bytes aligned
pucData ucLenDWNeed dwords long
*/
ULONG SSX31A_GetRng(ULONG ulPhyLink, UCHAR ucLenDWNeed, UCHAR* pucData, UCHAR* pucLenDW)
{
SSX31ADRV_CTRL * pDrvCtrl = (SSX31ADRV_CTRL *)ulPhyLink;
LONG lIntMask;
PEBD_DESC * pCurBD = NULL;
PERD_DESC * pCurRD = NULL;
ULONG ulCnt = 0;
ULONG i;
ULONG ulTmt = 0;
UCHAR ucRes = ERR;
SplImp(&lIntMask);
PciRead32(SSX31A_RNG_STAT_R, &ulCnt);
if ( ulCnt < ucLenDWNeed )
{
*pucLenDW = (UCHAR)ulCnt;
}
else
{
*pucLenDW = ucLenDWNeed;
}
if ( pDrvCtrl->ulCurrDMA1BdReadPtr == ((pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1)) )
{
#ifdef HI_DBG
PRINT("Queue full:BD Read:%d write %d\r\n",
pDrvCtrl->ulCurrDMA1BdReadPtr,
pDrvCtrl->ulCurrDMA1BdWritePtr );
#endif
return ERR;
}
pCurBD = &((PEBD_DESC *)(pDrvCtrl->ulDMA1BDMemBase))[pDrvCtrl->ulCurrDMA1BdWritePtr];
pCurBD->ulInputContext = NULL;
pCurBD->ulInputNum = 0;
pCurBD->ulInputLength= (*pucLenDW)*4;
pCurBD->ulGatherEnable &= ~BD_GATHER_ENABLE;
pCurBD->ulOutputContext = virt_to_bus ( (ULONG)pucData );
/* pCurBD->ulOutLen1 = ulCnt; */
pCurBD->ulOutputNum = 0;
pCurBD->ulScatterEnable &= ~BD_SCATTER_ENABLE;
pCurBD->ulOpCode = BD_OPCODE_RANDOMICITY_READ;
pCurBD->ulFlag = 0;
pDrvCtrl->ulCurrDMA1BdWritePtr = (pDrvCtrl->ulCurrDMA1BdWritePtr + 1) & (SSX31A_DMA1_BDQUEUE_LEN - 1);
PciWrite32(SSX31A_BQWP1_RW, pDrvCtrl->ulCurrDMA1BdWritePtr);
pDrvCtrl->ulFreeDMA1BDs --;
SplX(lIntMask);
ulTmt = (DMA1_TMOUT & 0xffff)*100 + 100000;
for (i = 0; i < ulTmt; i ++)
{
UsDelay(10);
PciRead32(SSX31A_BQRP1_RW, &pDrvCtrl->ulCurrDMA1BdReadPtr);
PciRead32(SSX31A_RQWP1_RW, &pDrvCtrl->ulCurrDMA1RdWritePtr);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
continue;
}
else
{
pCurRD = &((PERD_DESC*)(pDrvCtrl->ulDMA1RDMemBase))[pDrvCtrl->ulCurrDMA1RdReadPtr];
if ((pCurRD->ulStatus & MASK_RD_STATUS_ERRCODE) == RD_STATUS_RDVALID)
{
ucRes = OK;
}
else
{
#ifdef HI_DBG
PRINT("\r\nSSX31A Get RNG failed. RD status %04x", pCurRD->ulStatus);
#endif
ucRes = ERR;
}
pDrvCtrl->ulCurrDMA1RdReadPtr = (pDrvCtrl->ulCurrDMA1RdReadPtr + 1) & (SSX31A_DMA1_RDQUEUE_LEN - 1);
if (pDrvCtrl->ulCurrDMA1RdWritePtr == pDrvCtrl->ulCurrDMA1RdReadPtr)
{
PciWrite32(SSX31A_RQRP1_RW, pDrvCtrl->ulCurrDMA1RdReadPtr);
pDrvCtrl->ulFreeDMA1BDs ++;
break;
}
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