ssx31adrv.c

海思KEY驱动

#ifdef __cplusplus
extern "C" {
#endif

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>

#include <linux/slab.h>
#include <linux/delay.h>

#include "../def.h"
#include "SSX31ADrv.h"
  
/*
PRINT
ULONG... 
SplImp
SplX
PciWrite32
PciRead32
OK
ERR

*/

ULONG SSX31A_Reset(SSX31ADRV_CTRL* pDrvCtrl)
{
    ULONG ulTempID = 0x10;
    LONG  lIntmask = 0;

    
    SplImp(&lIntmask);

    PciWrite32(SSX31A_MC_MRID_RW, ulTempID | MASK_MC_MRID_RST);

    UsDelay(10);

    PciWrite32(SSX31A_MC_MRID_RW, ulTempID);
    
    PciRead32(SSX31A_MC_MRID_RW, &ulTempID);

    if ((ulTempID & 0xff) != 0x10)
    {
#ifdef HI_DBG    
        PRINT("SSX31A version err:%08x.\r\n", ulTempID);
#endif	
        return ERR;
    }

    SplX(lIntmask);

    return OK;
}



ULONG SSX31A_SDRAMInit(SSX31ADRV_CTRL* pDrvCtrl)
{
	ULONG ulWrite;
	ULONG ulRead;
	LONG  lIntmask = 0;

    SplImp(&lIntmask);
 
	PciWrite32(  0x0024, 0x00000003 );//clk_enable,add by xyr on 20050617
	
 	PciRead32(  SSX31A_MC_SDRAM_CTRL_RW, &ulRead );
	
 	ulWrite=ulRead | (0x80000000) ;
	
        PciWrite32(  SSX31A_MC_SDRAM_CTRL_RW, ulWrite );
	
	PciRead32(  SSX31A_MC_SDRAM_CTRL_RW, &ulRead );
	
 	UsDelay(10);
	
	ulWrite=ulRead & (0x7fffffff) ;
	
	PciWrite32(  SSX31A_MC_SDRAM_CTRL_RW, ulWrite );
	
	PciRead32(  SSX31A_MC_SDRAM_CTRL_RW, &ulRead );
/*	
	ulWrite=ulRead | (0x00100000) ; 9 
 	ulWrite=ulRead & (0xffe7ffff) ; 11 
*/

	ulRead=ulRead | (0x00080000) ; /* 10 */
 	ulWrite=ulRead & (0xffefffff) ;

        PciWrite32(  SSX31A_MC_SDRAM_CTRL_RW, ulWrite );


    SplX(lIntmask);

    return OK;
}

ULONG SSX31A_MemInit(SSX31ADRV_CTRL* pDrvCtrl)
{

    ULONG ulDMA1MemPoolSize;
    ULONG ulDMA2MemPoolSize;
    ULONG ulSize;

    /* DMA1 */
    pDrvCtrl->ulDMA1BDDescs = SSX31A_DMA1_BDQUEUE_LEN;
    pDrvCtrl->ulDMA1RDDescs = SSX31A_DMA1_RDQUEUE_LEN;

    ulDMA1MemPoolSize = pDrvCtrl->ulDMA1BDDescs * (SSX31A_BD_LENGTH) + pDrvCtrl->ulDMA1RDDescs * (SSX31A_RD_LENGTH);

	
    /* DMA2 */	
    pDrvCtrl->ulDMA2BDDescs = SSX31A_DMA2_BDQUEUE_LEN;
    pDrvCtrl->ulDMA2RDDescs = SSX31A_DMA2_RDQUEUE_LEN;

    ulDMA2MemPoolSize = pDrvCtrl->ulDMA2BDDescs * (SSX31A_BD_LENGTH) + pDrvCtrl->ulDMA2RDDescs * (SSX31A_RD_LENGTH);


    ulSize = ulDMA1MemPoolSize + ulDMA2MemPoolSize;


    pDrvCtrl->ulMemBase = (ULONG)Malloc( ulSize);
    if (pDrvCtrl->ulMemBase == NULL)
    {
#ifdef HI_DBG    
        PRINT("\r\nSSX31A memory Init failed.");
#endif	
        return ERR;
    }
    Mem_Set((VOID*)pDrvCtrl->ulMemBase, 0, ulSize);

    /* DMA1 memory info init */
    pDrvCtrl->ulDMA1BDMemBase      = pDrvCtrl->ulMemBase;
    pDrvCtrl->ulFreeDMA1BDs        = pDrvCtrl->ulDMA1BDDescs;
    pDrvCtrl->ulCurrDMA1BdReadPtr  = 0;
    pDrvCtrl->ulCurrDMA1BdWritePtr = 0;

    pDrvCtrl->ulDMA1RDMemBase      = pDrvCtrl->ulDMA1BDMemBase + pDrvCtrl->ulDMA1BDDescs * (SSX31A_BD_LENGTH);
    pDrvCtrl->ulFreeDMA1RDs        = pDrvCtrl->ulDMA1RDDescs;
    pDrvCtrl->ulCurrDMA1RdReadPtr  = 0;
    pDrvCtrl->ulCurrDMA1RdWritePtr = 0;


    /* DMA2 memory info init */
    pDrvCtrl->ulDMA2BDMemBase         = pDrvCtrl->ulMemBase + ulDMA1MemPoolSize;
    pDrvCtrl->ulFreeDMA2BDs           = pDrvCtrl->ulDMA2BDDescs;
    pDrvCtrl->ulCurrDMA2BdReadPtr     = 0;
    pDrvCtrl->ulCurrDMA2BdWritePtr    = 0;


    pDrvCtrl->ulDMA2RDMemBase         = pDrvCtrl->ulDMA2BDMemBase + pDrvCtrl->ulDMA2BDDescs * (SSX31A_BD_LENGTH);
    pDrvCtrl->ulFreeDMA2RDs           = pDrvCtrl->ulDMA2RDDescs;
    pDrvCtrl->ulCurrDMA2RdReadPtr     = 0;
    pDrvCtrl->ulCurrDMA2RdWritePtr    = 0;
    
    return OK;
}

ULONG SSX31A_DMAInit(SSX31ADRV_CTRL* pDrvCtrl)
{
    ULONG ulPciMemBase = 0;
    int iIntVal = 0;
    ULONG ulRead = 0;
    LONG lIntmask = 0;

    SplImp(&lIntmask);

    PciWrite32(SSX31A_BQBA1_RW, virt_to_bus(pDrvCtrl->ulDMA1BDMemBase) );
    PciWrite32(SSX31A_BQBA2_RW, virt_to_bus(pDrvCtrl->ulDMA2BDMemBase) );



    PciWrite32(SSX31A_BQS1_RW, (SSX31A_DMA1_BDQUEUE_LEN - 1));
    PciWrite32(SSX31A_BQS2_RW, (SSX31A_DMA2_BDQUEUE_LEN - 1));



    PciWrite32(SSX31A_BQRP1_RW, 0);
    PciWrite32(SSX31A_BQRP2_RW, 0);



    PciWrite32(SSX31A_BQWP1_RW, 0);
    PciWrite32(SSX31A_BQWP2_RW, 0);



    PciWrite32(SSX31A_RQBA1_RW, virt_to_bus(pDrvCtrl->ulDMA1RDMemBase) );
    PciWrite32(SSX31A_RQBA2_RW, virt_to_bus(pDrvCtrl->ulDMA2RDMemBase) );



    PciWrite32(SSX31A_RQS1_RW, SSX31A_DMA1_RDQUEUE_LEN  -1); 
    PciWrite32(SSX31A_RQS2_RW, SSX31A_DMA2_RDQUEUE_LEN  -1); 



    PciWrite32(SSX31A_RQRP1_RW, 0);
    PciWrite32(SSX31A_RQRP2_RW, 0);



    PciWrite32(SSX31A_RQWP1_RW, 0);
    PciWrite32(SSX31A_RQWP2_RW, 0);



    pDrvCtrl->ulCurrDMA1BdWritePtr = 0;
    pDrvCtrl->ulCurrDMA1BdReadPtr = 0;

    
    
    pDrvCtrl->ulCurrDMA1RdReadPtr = 0;
    pDrvCtrl->ulCurrDMA1RdWritePtr = 0;



    pDrvCtrl->ulCurrDMA2BdWritePtr = 0;
    pDrvCtrl->ulCurrDMA2BdReadPtr = 0;

    
    
    pDrvCtrl->ulCurrDMA2RdReadPtr = 0;
    pDrvCtrl->ulCurrDMA2RdWritePtr = 0;

    

    PciWrite32(SSX31A_BQTMOUT1_RW, DMA1_TMOUT ); 
    PciWrite32(SSX31A_BQTMOUT2_RW, DMA2_TMOUT ); 

     

    PciWrite32(SSX31A_MC_INT_CTRL0_RW, SSX31A_PE_INT_TIME_QUERY | SSX31A_PE_INT_PAKT_1 << 29);
    PciWrite32(SSX31A_MC_INT_CTRL1_RW, SSX31A_PE_INT_TIME_QUERY | SSX31A_PE_INT_PAKT_1 << 29);



    PciWrite32(SSX31A_PLDR1_RW, sizeof(PEBD_DESC)/4 );
    PciWrite32(SSX31A_PLDR2_RW, sizeof(PEBD_DESC)/4 );



    PciWrite32(SSX31A_DMA_CTRL1_RW, 
    	MASK_DMA_CTRL_EN | 
    	MASK_DMA_CTRL_MAX_BURST128 /*|
    	MASK_DMA_CTRL_BYTE_ODER_SWAP_DESC | 
    	MASK_DMA_CTRL_BYTE_ODER_SWAP_DATA*/ );
	
    PciWrite32(SSX31A_DMA_CTRL2_RW, 
    	MASK_DMA_CTRL_EN /*| 
    	MASK_DMA_CTRL_MAX_BURST128 /*| 
    	MASK_DMA_CTRL_BYTE_ODER_SWAP_DESC | 
    	MASK_DMA_CTRL_BYTE_ODER_SWAP_DATA*/ );



    SplX(lIntmask);


    return OK;
}

ULONG SSX31A_ISRInit(SSX31ADRV_CTRL* pDrvCtrl)
{
    return OK;
}





ULONG SSX31A_DeviceInit(SSX31ADRV_CTRL* pDrvCtrl)
{
 	if ( SSX31A_Reset ( pDrvCtrl ) == ERR )
	{
#ifdef HI_DBG	
		PRINT("\r\nReset SSX31A failed.");
#endif		
		return ERR;
	}
   
	if (SSX31A_SDRAMInit(pDrvCtrl) == ERR)
	{
#ifdef HI_DBG	
		PRINT("SSX31A SDRAM init failed. \r\n ");
#endif		
		return ERR;
	}
    
	if (SSX31A_MemInit(pDrvCtrl) == ERR)
	{
#ifdef HI_DBG	
		PRINT("SSX31A driver Mem init failed. \r\n ");
#endif		
		return ERR;
	}

	
	if (SSX31A_DMAInit(pDrvCtrl) == ERR)
	{
#ifdef HI_DBG	
		PRINT("SSX31A driver MODP init failed. \r\n ");
#endif		
		return ERR;
	}
    

	if (SSX31A_ISRInit(pDrvCtrl) == ERR)
	{
#ifdef HI_DBG	
		PRINT("SSX31A driver ISR init failed. \r\n ");
#endif		
		return ERR;
	}

	
	PciWrite32(SSX31A_RNG_CTRL_RW, 0x1083 );

    return OK;
}

VOID  SSX31A_Release(SSX31ADRV_CTRL *  pDrvCtrl)
{
	Free (pDrvCtrl->ulMemBase);
}

VOID SSX31A_ShowReg(SSX31ADRV_CTRL *  pDrvCtrl, UCHAR* pucBuffer)
{
    ULONG ulTmp, ulTmp1, ulTmp2, ulTmp3;
#define REG_ADDR(x) (x)


    PciRead32(SSX31A_MC_MRID_RW,        &ulTmp);
    PciRead32(SSX31A_MC_SDRAM_CTRL_RW,  &ulTmp1);
    PciRead32(SSX31A_MC_CYC_CNT_1US_RW, &ulTmp2);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "MRID",        REG_ADDR(SSX31A_MC_MRID_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "SDRAM_CTRL",  REG_ADDR(SSX31A_MC_SDRAM_CTRL_RW), ulTmp1);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "CYC_CNT_1US", REG_ADDR(SSX31A_MC_CYC_CNT_1US_RW),ulTmp2);    

    PciRead32(SSX31A_MC_INT_CTRL0_RW, &ulTmp);
    PciRead32(SSX31A_MC_INT_CTRL1_RW, &ulTmp3);
    PciRead32(SSX31A_MC_INT_MASK_RW,  &ulTmp1);
    PciRead32(SSX31A_PE_CTRL_RW,   &ulTmp2);
    
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "INT_CTRL0", REG_ADDR(SSX31A_MC_INT_CTRL0_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "INT_CTRL1", REG_ADDR(SSX31A_MC_INT_CTRL1_RW), ulTmp3);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "INT_MASK",  REG_ADDR(SSX31A_MC_INT_MASK_RW),  ulTmp1);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "PE_CTRL",   REG_ADDR(SSX31A_PE_CTRL_RW),   ulTmp2);

    PciRead32(SSX31A_BQBA1_RW, &ulTmp);
    PciRead32(SSX31A_BQS1_RW,  &ulTmp1);
    PciRead32(SSX31A_BQRP1_RW, &ulTmp2);
    PciRead32(SSX31A_BQWP1_RW, &ulTmp3);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQBA1", REG_ADDR(SSX31A_BQBA1_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQS1",  REG_ADDR(SSX31A_BQS1_RW),  ulTmp1);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQRP1", REG_ADDR(SSX31A_BQRP1_RW), ulTmp2);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQWP1", REG_ADDR(SSX31A_BQWP1_RW), ulTmp3);
   
    PciRead32(SSX31A_RQBA1_RW, &ulTmp);
    PciRead32(SSX31A_RQS1_RW,  &ulTmp1);
    PciRead32(SSX31A_RQRP1_RW, &ulTmp2);
    PciRead32(SSX31A_RQWP1_RW, &ulTmp3);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RQBA1", REG_ADDR(SSX31A_RQBA1_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RQS1",  REG_ADDR(SSX31A_RQS1_RW),  ulTmp1);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RQRP1", REG_ADDR(SSX31A_RQRP1_RW), ulTmp2);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "RQWP1", REG_ADDR(SSX31A_RQWP1_RW), ulTmp3);

  
    PciRead32(SSX31A_DMA_CTRL1_RW, &ulTmp);
    PciRead32(SSX31A_PLDR1_RW,    &ulTmp1);
    PciRead32(SSX31A_BQTMOUT1_RW, &ulTmp2);
 
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "DMACTRL1", REG_ADDR(SSX31A_DMA_CTRL1_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQTMOUT1", REG_ADDR(SSX31A_BQTMOUT1_RW), ulTmp2);
    
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "PDLR1",    REG_ADDR(SSX31A_PLDR1_RW),    ulTmp1);    




    PciRead32(SSX31A_BQBA2_RW, &ulTmp);
    PciRead32(SSX31A_BQS2_RW,  &ulTmp1);
    PciRead32(SSX31A_BQRP2_RW, &ulTmp2);
    PciRead32(SSX31A_BQWP2_RW, &ulTmp3);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQBA2", REG_ADDR(SSX31A_BQBA2_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQS2",  REG_ADDR(SSX31A_BQS2_RW),  ulTmp1);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQRP2", REG_ADDR(SSX31A_BQRP2_RW), ulTmp2);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQWP2", REG_ADDR(SSX31A_BQWP2_RW), ulTmp3);
    
    PciRead32(SSX31A_RQBA2_RW, &ulTmp);
    PciRead32(SSX31A_RQS2_RW,  &ulTmp1);
    PciRead32(SSX31A_RQRP2_RW, &ulTmp2);
    PciRead32(SSX31A_RQWP2_RW, &ulTmp3);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RQBA2", REG_ADDR(SSX31A_RQBA2_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RQS2",  REG_ADDR(SSX31A_RQS2_RW),  ulTmp1);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RQRP2", REG_ADDR(SSX31A_RQRP2_RW), ulTmp2);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "RQWP2", REG_ADDR(SSX31A_RQWP2_RW), ulTmp3);

    
    PciRead32(SSX31A_DMA_CTRL2_RW, &ulTmp);
    PciRead32(SSX31A_PLDR2_RW,    &ulTmp1);
    PciRead32(SSX31A_BQTMOUT2_RW, &ulTmp2);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "DMACTRL2", REG_ADDR(SSX31A_DMA_CTRL2_RW), ulTmp);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "BQTMOUT2", REG_ADDR(SSX31A_BQTMOUT2_RW), ulTmp2);


    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "PDLR2",    REG_ADDR(SSX31A_PLDR2_RW),    ulTmp1);



    
    PciRead32(SSX31A_RNG_CTRL_RW, &ulTmp);
    PciRead32(SSX31A_RNG_STAT_R,    &ulTmp1);
    PciRead32(SSX31A_RNG_TEST_R,    &ulTmp2);

    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RNG_CTRL", REG_ADDR(SSX31A_RNG_CTRL_RW), ulTmp);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x", "RNG_STAT",    REG_ADDR(SSX31A_RNG_STAT_R),    ulTmp1);
    pucBuffer += SPRINTF(pucBuffer, "\r\n%20s(%04x):%08x\n", "RNG_TEST",    REG_ADDR(SSX31A_RNG_TEST_R),    ulTmp2);

}

ULONG  SSX31A_ReadReg(SSX31ADRV_CTRL *  pDrvCtrl, ULONG ulOff, ULONG* pulValue)
{
	PciRead32(ulOff, pulValue);

    return OK;
}
ULONG  SSX31A_WriteReg(SSX31ADRV_CTRL *  pDrvCtrl, ULONG ulOff, ULONG ulValue )
{
	PciWrite32(ulOff, ulValue);  

  return OK;	
}






#ifdef __cplusplus 
}
#endif