📄 ssx31adrv.h
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#ifndef _SSX31ADRV_H_
#define _SSX31ADRV_H_
/***********************************************************************************/
#define DMA1_TMOUT 0x0BB80BB8
#define DMA2_TMOUT 0x0BB80BB8
#define BD_OPCODE_DH_PUBLICKEY_PRODUCT 0x00
#define BD_OPCODE_DH_PRIVATEKEY_PRODUCT 0x01
#define BD_OPCODE_RSA_PUBLICKEY_OPERATION 0x02
#define BD_OPCODE_RSA_PRIVATEKEY_OPERATION 0x03
#define BD_OPCODE_DSA_IDIOGRAPH_OPERATION 0x04
#define BD_OPCODE_DSA_VALIDATE_OPERATION 0x05
#define BD_OPCODE_MODULE_ADD 0x40
#define BD_OPCODE_MODULE_SUBTRACT 0x41
#define BD_OPCODE_MODULE_MULTIPLY 0x42
#define BD_OPCODE_MODULE_GET 0x43
#define BD_OPCODE_MODULE_POWER 0x44
#define BD_OPCODE_DOUBLE_MODULE_POWER 0x45
#define BD_OPCODE_SA_UPDATE 0x80
#define BD_OPCODE_SA_READ 0x81
#define BD_OPCODE_DES_OPERATION 0x82
#define BD_OPCODE_HASH_OPERATION 0x83
#define BD_OPCODE_RANDOMICITY_READ 0x84
#define BD_OPCODE_IPSEC 0xc0
#define BD_OPCODE_IPSEC_BACK 0xc1
#define BD_FLAG_ENCRYPT 0x01
#define BD_FLAG_DECRYPT 0x00
#define BD_FLAG_DES 0x00
#define BD_FLAG_3DES 0x02
#define BD_FLAG_MD5 0x08
#define BD_FLAG_SHA1 0x0a
#define BD_FLAG_HMAC_MD5 0x0c
#define BD_FLAG_HMAC_SHA1 0x0e
#define BD_FLAG_ECB 0x00
#define BD_FLAG_CBC 0x10
#define BD_GATHER_ENABLE 0x01
#define BD_SCATTER_ENABLE 0x01
#define MASK_RD_STATUS_VALID 0x80000000
#define MASK_RD_STATUS_ERRCODE 0xffff0000
#define RD_STATUS_RDVALID 0
#define RD_STATUS_DMA1_DMALEN_ERR 0x0002
#define RD_STATUS_DMA1_OPCODE_ERR 0x0003
#define RD_STATUS_DMA1_PE_TMOUT 0x0100
#define RD_STATUS_DMA1_BDLEN_ERR 0x0200
#define RD_STATUS_DMA1_INLEN_ERR 0x0400
#define RD_STATUS_DMA2_MOD0_ERR 0x0001
#define RD_STATUS_DMA2_MODLEN_ERR 0x0002
#define RD_STATUS_DMA2_PKEOPCODE_ERR 0x0004
#define RD_STATUS_DMA2_EXPONENT0_ERR 0x0008
#define RD_STATUS_DMA2_EXPONENT1_ERR 0x0010
#define RD_STATUS_DMA2_PE_TMOUT 0x0100
#define RD_STATUS_DMA2_BDLEN_ERR 0x0200
#define RD_STATUS_DMA2_INLEN_ERR 0x0400
#define RD_STATUS_DMA3_PE_TMOUT 0x7000
#define RD_STATUS_DMA3_OPCODE_ERR 0x1000
#define RD_STATUS_DMA3_INLEN_ERR 0x2000
#define RD_STATUS_DMA3_TOTALLEN_ERR 0x3000
#define RD_STATUS_DMA3_SOFT_FLOW_ERR 0x0400
#define RD_STATUS_DMA3_HARD_FLOW_ERR 0x0200
#define RD_STATUS_DMA3_SEQNUM_ERR 0x0100
#define RD_STATUS_DMA3_ICV_ERR 0x0080
#define RD_STATUS_DMA3_PAD_ERR 0x0040
#define RD_STATUS_DMA3_PKTSTRUCT_ERR 0x0020
#define RD_STATUS_DMA3_IPFRAGMENT_ERR 0x0003
#define RD_STATUS_DMA3_PKTSTRUCT_ERR2 0x0011
#define RD_STATUS_DMA3_OPTION_ERR 0x0012
#define RD_STATUS_DMA3_SAINVALID_ERR 0x0013
#define RD_STATUS_DMA3_SPI_ERR 0x0014
#define RD_STATUS_DMA3_SEQNUM_ERR2 0x0015
#define RD_STATUS_DMA3_SOFT_FLOW_ERR2 0x0016
#define RD_STATUS_DMA3_HARD_FLOW_ERR2 0x0017
#define RD_STATUS_DMA3_ALIGN_ERR 0x0018
#define RD_STATUS_DMA3_ICV_ERR2 0x0019
#define RD_STATUS_DMA3_PAD_ERR2 0x001b
#define ICD_ATTRIB_LAST_PART 0xff
#define ICD_ATTRIB_NOT_LAST_PART 0x00
#define ICD_DATASRC_SOFT_OFFER 0x00
#define ICD_DATASRC_CHIP_PRODUCT 0x01
#define ICD_DATASRC_USE_LAST_OPERATOR 0x03
#define ICD_DATASRC_USE_LAST_RESULT 0x02
#define ICD_DATASRC_OFFER_HASH_PKT 0x04
/***********************************************************************************/
#define SSX31A_MC_MRID_RW 0x0000
#define SSX31A_MC_SDRAM_CTRL_RW 0x0004
#define SSX31A_MC_INT_CTRL0_RW 0x0008
#define SSX31A_MC_INT_CTRL1_RW 0x000c
#define SSX31A_MC_INT_STAT_R 0x0010
#define SSX31A_MC_INT_MASK_RW 0x0014
#define SSX31A_MC_CYC_CNT_1US_RW 0x0018
#define SSX31A_MC_SDRAM_TEST_RW 0x00f0
#define SSX31A_MC_GPIO_REG_RW 0x00f4
#define SSX31A_PE_CTRL_RW 0x1000
#define SSX31A_AES_CTR_INIT_RW 0x1004
#define SSX31A_TIMER_HIGH_R 0x1008
#define SSX31A_TIMER_LOW_R 0x100c
#define SSX31A_LFSR_INIT_VALUE 0x1020
#define SSX31A_PLL_RST_RW 0x0200
#define SSX31A_PLL0_CTRL_RW 0x0204
#define SSX31A_PLL1_CTRL_RW 0x0208
#define SSX31A_BQBA1_RW 0x2100
#define SSX31A_BQS1_RW 0x2104
#define SSX31A_BQRP1_RW 0x2108
#define SSX31A_BQWP1_RW 0x210c
#define SSX31A_RQBA1_RW 0x2110
#define SSX31A_RQS1_RW 0x2114
#define SSX31A_RQRP1_RW 0x2118
#define SSX31A_RQWP1_RW 0x211c
#define SSX31A_DMA_CTRL1_RW 0x2120
#define SSX31A_PLDR1_RW 0x2124
#define SSX31A_BQTMOUT1_RW 0x2128
#define SSX31A_BQBA2_RW 0x2200
#define SSX31A_BQS2_RW 0x2204
#define SSX31A_BQRP2_RW 0x2208
#define SSX31A_BQWP2_RW 0x220c
#define SSX31A_RQBA2_RW 0x2210
#define SSX31A_RQS2_RW 0x2214
#define SSX31A_RQRP2_RW 0x2218
#define SSX31A_RQWP2_RW 0x221c
#define SSX31A_DMA_CTRL2_RW 0x2220
#define SSX31A_PLDR2_RW 0x2224
#define SSX31A_BQTMOUT2_RW 0x2228
#define SSX31A_RNG_CTRL_RW 0x4000
#define SSX31A_RNG_STAT_R 0x4008
#define SSX31A_RNG_TEST_R 0x400c
#define MASK_MC_MRID_RST 0x80000000
#define MASK_MC_MRID_VERSION_ID 0x000000ff
#define mask_ecrp_xst 0x04000000
#define mask_ehash_xst 0x08000000
#define mask_iv_hold_mode 0x20000000
#define mask_test_iv_gen 0x80000000
#define SSX31A_PE_INT_TIME_QUERY 1000
#define SSX31A_PE_INT_PAKT_1 0x0
#define SSX31A_PE_PROTO_TMOUT 10000
#define SSX31A_PE_INT_PAKT_4 0x20000000
#define SSX31A_PE_INT_PAKT_8 0x40000000
#define SSX31A_PE_INT_PAKT_16 0x60000000
#define SSX31A_PE_INT_PAKT_32 0x80000000
#define SSX31A_PE_INT_PAKT_64 0xa0000000
#define SSX31A_PE_INT_PAKT_128 0xc0000000
#define SSX31A_PE_INT_PAKT_256 0xe0000000
#define MASK_INT_DMA1_PACKETOP_DONE 0x00000001
#define MASK_INT_DMA1_READBD_DONE 0x00000002
#define MASK_INT_DMA1_RDQ_FULL 0x00000004
#define MASK_INT_DMA1_PRO_TIMEOUT 0x00000008
#define MASK_INT_DMA2_PACKETOP_DONE 0x00000100
#define MASK_INT_DMA2_READBD_DONE 0x00000200
#define MASK_INT_DMA2_RDQ_FULL 0x00000400
#define MASK_INT_DMA2_PRO_TIMEOUT 0x00000800
#define MASK_INT_DMA3_PACKETOP_DONE 0x00010000
#define MASK_INT_DMA3_READBD_DONE 0x00020000
#define MASK_INT_DMA3_RDQ_FULL 0x00040000
#define MASK_INT_DMA3_PRO_TIMEOUT 0x00080000
#define MASK_INT_OSC_FAIL 0x01000000
#define MASK_DMA_CTRL_EN 0x00000001
#define MASK_DMA_CTRL_MAX_BURST32 0x00000000
#define MASK_DMA_CTRL_MAX_BURST64 0x00000002
#define MASK_DMA_CTRL_MAX_BURST128 0x00000004
#define MASK_DMA_CTRL_MAX_BURST256 0x00000006
#define MASK_DMA_CTRL_BIT_ODER_SWAP_DATA 0x00000008
#define MASK_DMA_CTRL_BYTE_ODER_SWAP_DATA 0x00000010
#define MASK_DMA_CTRL_BYTE_ODER_SWAP_DESC 0x00000020
#define MASK_DMA_CTRL_RESV_HIGH 0xffffffc0
#define MASK_RNG_ENABLE 0x00000001
#define SSX31A_DMA1_BDQUEUE_LEN 512
#define SSX31A_DMA1_RDQUEUE_LEN 512
#define SSX31A_DMA2_BDQUEUE_LEN 512
#define SSX31A_DMA2_RDQUEUE_LEN 512
/*********************************************************************************************/
typedef struct tagPeBdDesc
{
ULONG ulFlag:8,
ulOpCode:8,
ulReserve:16;
ULONG ulInputContext;
ULONG ulInputLength:20,
ulReserve1:6,
ulGatherEnable:1,
ulInputNum:5;
ULONG ulOutputContext;
ULONG ulOutputLength0:16,
ulOutputLength1:10,
ulScatterEnable:1,
ulOutputNum:5;
ULONG ulID;
} PEBD_DESC;
#define SSX31A_BD_LENGTH sizeof(PEBD_DESC)
typedef struct tagPeRdDesc
{
ULONG ulFlag:8,
ulOpCode:8,
ulStatus:16;
ULONG ulInputContext;
ULONG ulInputLength:20,
ulReserve1:6,
ulGatherEnable:1,
ulInputNum:5;
ULONG ulOutputContext;
ULONG ulOutputLength0:16,
ulOutputLength1:10,
ulScatterEnable:1,
ulOutputNum:5;
ULONG ulID;
} PERD_DESC;
#define SSX31A_RD_LENGTH sizeof(PERD_DESC)
/***************************************************************************************/
/* ICD 结构 */
/***************************************************************************************/
typedef struct tagInContextDesc
{
ULONG ulInputPtr;
ULONG ulInputLen:16,
ulOrig:8,
ulInputAttrib:8;
} SSX31A_ICD;
/***************************************************************************************/
/* OCD 结构 */
/***************************************************************************************/
typedef struct tagScatterParticle
{
ULONG ulOutputPtr;
ULONG ulOutputLen:16,
ulOrig:8,
ulOutputAttrib:8;
} SSX31A_OCD;
typedef struct tagSsx31adrvctrl
{
struct pci_dev * pPciDev;
ULONG phymembase;
CHAR pchName[50];
ULONG ulPciMemBase; /* PCI mem base */
ULONG ulMemBase; /* IPSec BD、RD descs memory pool base */
ULONG ulDMA1BDMemBase;
ULONG ulDMA1BDDescs;
ULONG ulFreeDMA1BDs;
ULONG ulCurrDMA1BdWritePtr;
ULONG ulCurrDMA1BdReadPtr;
ULONG ulDMA1RDMemBase;
ULONG ulDMA1RDDescs;
ULONG ulFreeDMA1RDs;
ULONG ulCurrDMA1RdReadPtr;
ULONG ulCurrDMA1RdWritePtr;
ULONG ulDMA2BDMemBase;
ULONG ulDMA2BDDescs;
ULONG ulFreeDMA2BDs;
ULONG ulCurrDMA2BdWritePtr;
ULONG ulCurrDMA2BdReadPtr;
ULONG ulDMA2RDMemBase;
ULONG ulDMA2RDDescs;
ULONG ulFreeDMA2RDs;
ULONG ulCurrDMA2RdReadPtr;
ULONG ulCurrDMA2RdWritePtr;
} SSX31ADRV_CTRL;
#endif
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