ssx31bsa.c

海思KEY驱动

#include <linux/config.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/ioport.h>
#include <linux/errno.h>

#include <linux/slab.h>
#include <linux/delay.h>


#include "../def.h"
#include "SSX31BDrv.h"
#include "SSX31BSA.h"
#include "../SSX31.h"

extern ULONG four_bytes_align_en(ULONG ulBusAddr, ULONG ulVirAddr);

ULONG SSX31B_SendSA(SSX31BDRV_CTRL *  pDrvCtrl, dma_addr_t p_CardSA_dma_phys, ULONG ulsaid)
{

    ULONG ulSaID, ulTemp, ulRes, i;
    LONG  lIntMask;
    SSX31B_BASIC_BD * pCurSaBD = NULL;
    ULONG ulTmt = 0;
    ulRes = ERR;


    ulSaID = ulsaid;

    SplImp(&lIntMask);


    if (pDrvCtrl->ulCurrSaBdReadPtr == ((pDrvCtrl->ulCurrSaBdWritePtr + 1) & (SSX31B_SA_BDQUEUE_LEN - 1)))
    {
        PRINT("BD Queue full:BD Read:%d write %d\r\n",
            pDrvCtrl->ulCurrSaBdReadPtr,
            pDrvCtrl->ulCurrSaBdWritePtr);
        return ulRes;
    }

    pCurSaBD = &((SSX31B_BASIC_BD *)(pDrvCtrl->ulSaBDMemBase))[pDrvCtrl->ulCurrSaBdWritePtr];


    pCurSaBD->ulOpCode = SSX31B_OPER_SA_UPDATE;
//    pCurSaBD->ulInputContext = virt_to_bus ((ULONG)p_CardSA);
    pCurSaBD->ulInputContext = (ULONG)p_CardSA_dma_phys;
	
    pCurSaBD->ulInputLength =  32*4;
    pCurSaBD->ulOutputContext = ulSaID;
    

    pDrvCtrl->ulCurrSaBdWritePtr = (pDrvCtrl->ulCurrSaBdWritePtr + 1) & (SSX31B_SA_BDQUEUE_LEN - 1);
    PciWrite32(SSX31B_REG_BQWP1, pDrvCtrl->ulCurrSaBdWritePtr);

    pDrvCtrl->ulFreeSaBDs --;

    SplX(lIntMask);

    ulTmt = (DMA1_TIMEOUT_DMA1)*100 + 100000;

    for (i = 0; i < ulTmt; i ++)
    {
        UsDelay(10);


        PciRead32(SSX31B_REG_BQRP1, &pDrvCtrl->ulCurrSaBdReadPtr);
        

        PciRead32(SSX31B_REG_RQWP1, &pDrvCtrl->ulCurrSaRdWritePtr);


        if (pDrvCtrl->ulCurrSaRdWritePtr == pDrvCtrl->ulCurrSaRdReadPtr)
        {
            continue;
        }
        else
        {

            pDrvCtrl->ulCurrSaRdReadPtr = (pDrvCtrl->ulCurrSaRdReadPtr + 1) & (SSX31B_SA_RDQUEUE_LEN - 1);  



            if (pDrvCtrl->ulCurrSaRdWritePtr == pDrvCtrl->ulCurrSaRdReadPtr)
            {

                PciWrite32(SSX31B_REG_RQRP1, pDrvCtrl->ulCurrSaRdReadPtr); 

               pDrvCtrl->ulFreeSaBDs ++;
               pDrvCtrl->ulTmtSADone ++;

                ulRes = OK;
                break;
            }

        }

    }

    if (i >= ulTmt)
    {
#ifdef HI_DBG    
    	PRINT ("\r\nnot finish");
#endif	
	ulRes = ERR;
    }


    return ulRes;
}


ULONG SSX31B_GetSA(SSX31BDRV_CTRL *  pDrvCtrl, ULONG ulsaid, dma_addr_t pucSA_dma_phys)
{
    ULONG ulSaID, ulRes, i;
    LONG  lIntMask;
    SSX31B_BASIC_BD * pCurSaBD = NULL;
    SSX31B_BASIC_RD * pCurSaRD = NULL;
    
    ulRes = ERR;
    ULONG ulTmt = 0;

    ulSaID = ulsaid;

    SplImp(&lIntMask);


    if (pDrvCtrl->ulCurrSaBdReadPtr == ((pDrvCtrl->ulCurrSaBdWritePtr + 1) & (SSX31B_SA_BDQUEUE_LEN - 1)))
    {
        PRINT("BD Queue full:BD Read:%d write %d\r\n",
            pDrvCtrl->ulCurrSaBdReadPtr,
            pDrvCtrl->ulCurrSaBdWritePtr);
        return ulRes;
    }

    pCurSaBD = &((SSX31B_BASIC_BD *)(pDrvCtrl->ulSaBDMemBase))[pDrvCtrl->ulCurrSaBdWritePtr];


    pCurSaBD->ulOpCode = SSX31B_OPER_SA_GET;
//    pCurSaBD->ulOutputContext = virt_to_bus ((ULONG)pucSA);
    pCurSaBD->ulOutputContext = (ULONG)pucSA_dma_phys;
    pCurSaBD->ulInputContext = ulSaID;
    pCurSaBD->ulInputLength = 1;



    pDrvCtrl->ulCurrSaBdWritePtr = (pDrvCtrl->ulCurrSaBdWritePtr + 1) & (SSX31B_SA_BDQUEUE_LEN - 1);
    PciWrite32(SSX31B_REG_BQWP1, pDrvCtrl->ulCurrSaBdWritePtr);

    pDrvCtrl->ulFreeSaBDs --;

    SplX(lIntMask);

    ulTmt = (DMA1_TIMEOUT_DMA1)*100 + 100000;

    for (i = 0; i < ulTmt; i ++)
    {
        UsDelay(10);


        PciRead32(SSX31B_REG_BQRP1, &pDrvCtrl->ulCurrSaBdReadPtr);
        

        PciRead32(SSX31B_REG_RQWP1, &pDrvCtrl->ulCurrSaRdWritePtr);


        if (pDrvCtrl->ulCurrSaRdWritePtr == pDrvCtrl->ulCurrSaRdReadPtr)
        {
            continue;
        }
        else
        {
            pCurSaRD = &((SSX31B_BASIC_RD*)(pDrvCtrl->ulSaRDMemBase))[pDrvCtrl->ulCurrSaRdReadPtr];

            if ((pCurSaRD->ulStatus & DMA1_ERR_MASK) == MDA1_STATUS_OK)
            {
               
            }
            else
            {
                PRINT("\r\nSSX31B Get SA failed");
            }
        

            pDrvCtrl->ulCurrSaRdReadPtr = (pDrvCtrl->ulCurrSaRdReadPtr + 1) & (SSX31B_SA_RDQUEUE_LEN - 1);  



            if (pDrvCtrl->ulCurrSaRdWritePtr == pDrvCtrl->ulCurrSaRdReadPtr)
            {

                PciWrite32(SSX31B_REG_RQRP1, pDrvCtrl->ulCurrSaRdReadPtr); 

                pDrvCtrl->ulFreeSaBDs ++;

                pDrvCtrl->ulTmtSADone ++;

                ulRes = OK;
                break;
            }

        }

    }


    if (i >= ulTmt)
    {
#ifdef HI_DBG    
    	PRINT ("\r\nnot finish");
#endif	
	ulRes = ERR;
    }

    return ulRes;
}

ULONG SSX31B_PhyUpdateSA(ULONG ulPhyLink, UCHAR* pstCardSA, dma_addr_t pstCardSA_dma_phys, ULONG ulSaNum)
{
    SSX31BDRV_CTRL * pDrvCtrl = (SSX31BDRV_CTRL *)ulPhyLink;
  

    if ( ERR== SSX31B_SendSA(pDrvCtrl, pstCardSA_dma_phys, ulSaNum))
    {
        PRINT("IPSec_SendSA2Secp: IPSec_SendSA() fail");
        return ERR;
    }
    //PRINT ( "SSX31B_SendSA OK!" );

#ifdef HI_DBG
    {
            int i,diff;
     	    ULONG *szSA ;
			
	   ULONG pucSA_dma_phys;
//	    UCHAR szBuf1[160] = {0};
//	    UCHAR* szBuf = (UCHAR*) szBuf1;	    
            UCHAR *pucSA = (UCHAR *)consistent_alloc(GFP_KERNEL|GFP_DMA,PAGE_SIZE,&pucSA_dma_phys); 
            memset(pucSA,0,160);
	diff= four_bytes_align_en( pucSA_dma_phys, (ULONG)pucSA) - (ULONG)pucSA;
	    
    	if ( ERR == SSX31B_GetSA(pDrvCtrl, ulSaNum, (ULONG)pucSA_dma_phys+diff) )
    	{
	        PRINT("\r\nIPSec_SendSA2Secp: IPSec_GetSA() fail");
	      consistent_free((void *)pucSA,PAGE_SIZE,(dma_addr_t)pucSA_dma_phys);
	        return ERR;
    	}
		
    	if (memcmp (pstCardSA, pucSA+diff, 32*4) == 0 )
    	{
    		//PRINT("\r\nIPSEC SA [%d] Update Success!",ulSaNum);
    	}
    	else
    	{
    		PRINT("\r\nIPSEC SA Update fail!");

            PRINT("\r\nSA writed:");
    		szSA = (ULONG*)pstCardSA;
	        for(i = 0; i < 32; i+=4)
	        {
	            PRINT("\r\n0x%08x 0x%08x 0x%08x 0x%08x", 
	            	szSA[i], szSA[i+1], szSA[i+2], szSA[i+3] );
	        }
		
            PRINT("\r\nSA read:");
            szSA = (ULONG *)(pucSA+diff);
            for(i = 0; i < 32; i+=4)
            {
	            PRINT("\r\n0x%08x 0x%08x 0x%08x 0x%08x",
                	szSA[i], szSA[i+1], szSA[i+2], szSA[i+3] );
            }
    		
    	}
      consistent_free((void *)pucSA,PAGE_SIZE,(dma_addr_t)pucSA_dma_phys);
    		
    }
#endif
    return OK;
    
}
/****************************************************** RNG ************************************************/
/****************************************************** RNG ************************************************/
/****************************************************** RNG ************************************************/
/*
pucData  4 bytes aligned
pucData  ucLenDWNeed dwords long
*/
ULONG SSX31B_GetRng(ULONG ulPhyLink, ULONG ucLenDWNeed, UCHAR* pucData, UCHAR* pucLenDW)
{
	
    SSX31BDRV_CTRL *  pDrvCtrl = (SSX31BDRV_CTRL *)ulPhyLink;
    LONG  lIntMask;
    SSX31B_BASIC_BD * pCurBD = NULL;
    SSX31B_BASIC_RD * pCurRD = NULL;
    ULONG ulCnt = 0;
    ULONG i;
    ULONG ulTmt = 0;
    UCHAR ucRes = ERR;
    
    
    SplImp(&lIntMask);
    
    PciRead32(SSX31B_REG_RNG_STAT, &ulCnt);
    
    i = 0;
    while (ulCnt < 100)
    {
    	if (i >= 1000)
	{
		return ERR;
	}
    	
    	udelay(10);
	PciRead32(SSX31B_REG_RNG_STAT, &ulCnt);
	
	i++;
    }
    
    if ( ulCnt < ucLenDWNeed )
    {
    	*pucLenDW = (UCHAR)ulCnt;
    }
    else
    {
    	*pucLenDW = ucLenDWNeed;
    }
    
    if ( pDrvCtrl->ulCurrSaBdReadPtr == ((pDrvCtrl->ulCurrSaBdWritePtr + 1) & (SSX31B_SA_BDQUEUE_LEN - 1)) )
    {
#ifdef HI_DBG    
        PRINT("Queue full:BD Read:%d write %d\r\n",
            pDrvCtrl->ulCurrSaBdReadPtr,
            pDrvCtrl->ulCurrSaBdWritePtr );
#endif	    
	    
        return ERR;
    }

    pCurBD = &((SSX31B_BASIC_BD *)(pDrvCtrl->ulSaBDMemBase))[pDrvCtrl->ulCurrSaBdWritePtr];


    pCurBD->ulInputContext  = 0;  
    pCurBD->ulInputNum = 0;
    pCurBD->ulInputLength= (*pucLenDW)*4;
    pCurBD->ulGatherEnable &= ~CD_GATHER_ENABLE;    


    pCurBD->ulOutputContext = virt_to_bus ( (ULONG)pucData );
    /* pCurBD->ulOutLen1 = ulCnt; */
    pCurBD->ulOutputNum  = 0;
    pCurBD->ulScatterEnable &= ~CD_SCATTER_ENABLE;


    pCurBD->ulOpCode = SSX31B_OPER_RANDOM_GET;
    pCurBD->ulFlag = 0;
    

   
    pDrvCtrl->ulCurrSaBdWritePtr = (pDrvCtrl->ulCurrSaBdWritePtr + 1) & (SSX31B_SA_BDQUEUE_LEN - 1);
    PciWrite32(SSX31B_REG_BQWP1, pDrvCtrl->ulCurrSaBdWritePtr);

    pDrvCtrl->ulFreeSaBDs --;

    SplX(lIntMask);    

    ulTmt = (DMA1_TIMEOUT_DMA1 & 0xffff)*100 + 100000;

    for (i = 0; i < ulTmt; i ++)
    {
        UsDelay(10);


        PciRead32(SSX31B_REG_BQRP1, &pDrvCtrl->ulCurrSaBdReadPtr);
        

        PciRead32(SSX31B_REG_RQWP1, &pDrvCtrl->ulCurrSaRdWritePtr);


        if (pDrvCtrl->ulCurrSaRdWritePtr == pDrvCtrl->ulCurrSaRdReadPtr)
        {
            continue;
        }
        else
        {
            pCurRD = &((SSX31B_BASIC_RD*)(pDrvCtrl->ulSaRDMemBase))[pDrvCtrl->ulCurrSaRdReadPtr];

            if ((pCurRD->ulStatus & DMA1_ERR_MASK) == MDA1_STATUS_OK)
            {
               ucRes = OK;   
            }
            else
            {
#ifdef HI_DBG	    
                PRINT("\r\nSSX31B Get RNG failed. RD status %04x", pCurRD->ulStatus);
#endif		
		ucRes = ERR;
            }
        
            pDrvCtrl->ulCurrSaRdReadPtr = (pDrvCtrl->ulCurrSaRdReadPtr + 1) & (SSX31B_SA_RDQUEUE_LEN - 1); 


	    if (pDrvCtrl->ulCurrSaRdWritePtr == pDrvCtrl->ulCurrSaRdReadPtr)
            {

                PciWrite32(SSX31B_REG_RQRP1, pDrvCtrl->ulCurrSaRdReadPtr);
                pDrvCtrl->ulFreeSaBDs ++;

                break;
            }

        }

    }
    if (i >= ulTmt)
    {
#ifdef HI_DBG    
    	PRINT ("\r\nnot finish");
#endif	
	ucRes = ERR;
    }


    return ucRes;
}